公开(公告)号：US20230262980A1

公开(公告)日：2023-08-17

申请号：US17936473

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjae Sim ,  Byung-Sun Park ,  Jaechul Lee ,  Dae-Hun Choi

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: Disclosed are a three-dimensional semiconductor memory device, a method of fabricating the same, and an electronic system including the same. The semiconductor memory device may include a substrate including a first region and a second region, a plurality of stacks including first and second stacks, each of which includes interlayer insulating layers and gate electrodes stacked alternately with the interlayer insulating layers on the substrate and has a stepped structure on the second region, an insulating layer on stepped structure of the first stack, a plurality of vertical channel structures provided on the first region to penetrate the first stack, and a separation structure separating the first and second stacks from each other. The insulating layer may include one or more dopants, and a dopant concentration of the insulating layer may decrease as a distance from the substrate increases.

公开(公告)号：US09312270B2

公开(公告)日：2016-04-12

申请号：US14593221

申请日：2015-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Tae Jang ,  Myoungbum Lee ,  Seungmok Shin ,  JinGyun Kim ,  Yeon-Sil Sohn ,  Seung-Yup Lee ,  Dae-Hun Choi

IPC: H01L21/00 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/8239 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about −0.1×109 dyne/cm2 to about −10×109 dyne/cm2 to the substrate.

Abstract translation: 提供制造三维半导体器件的方法。 该方法包括：在基板上形成薄膜结构，其中至少2n（n是大于2的整数）的第一和第二材料层交替重复堆叠; 其中所述第一材料层向所述基板施加约0.1×10 9达因/ cm 2至约10×10 9达因/ cm 2的范围内的应力，并且所述第二材料层施加约-0.1×109达因/ cm2的范围内的应力 至约-10×109达因/平方厘米。