公开(公告)号：US20240341094A1

公开(公告)日：2024-10-10

申请号：US18522352

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoun Seo ,  Daeho Kim ,  Su Jong Kim ,  Sangho Rha ,  Byung-Sun Park ,  Mingyu Jeon

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/0651

Abstract: A semiconductor device may include a substrate including a cell array region and a connection region, a stack including electrodes, which are vertically stacked on the substrate, and which have a staircase structure in the connection region, channel regions provided on the cell array region that vertically extend through the stack, and a planarization insulating layer that covers the stack in the connection region. The planarization insulating layer may include a first insulating layer in contact with the stack and a second insulating layer that covers the first insulating layer. The first insulating layer may include high-density plasma (HDP) oxide, which is doped with first dopants, and the second insulating layer may include tetraethyl orthosilicate (TEOS) oxide, which is doped with second dopants.

公开(公告)号：US11225715B2

公开(公告)日：2022-01-18

申请号：US16750557

申请日：2020-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Sun Park ,  Ik Soo Kim ,  Jiwoon Im ,  Sangho Rha ,  Minjae Oh

IPC: C23C16/455 ,  H01L21/67 ,  H01J37/32

Abstract: A semiconductor manufacturing apparatus includes a chamber that includes a station in which a substrate is provided, a substrate holder that is in the station and receives the substrate, and lower showerheads below the substrate holder, the lower showerheads including an isotropic showerhead having first nozzle holes that isotropically provide a first reaction gas on a bottom surface of the substrate, and a striped showerhead having striped nozzle regions and striped blank regions between the striped nozzle regions, the striped nozzle regions having second nozzle holes that non-isotropically provide a second reaction gas on the bottom surface of the substrate.

公开(公告)号：US20230262980A1

公开(公告)日：2023-08-17

申请号：US17936473

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjae Sim ,  Byung-Sun Park ,  Jaechul Lee ,  Dae-Hun Choi

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: Disclosed are a three-dimensional semiconductor memory device, a method of fabricating the same, and an electronic system including the same. The semiconductor memory device may include a substrate including a first region and a second region, a plurality of stacks including first and second stacks, each of which includes interlayer insulating layers and gate electrodes stacked alternately with the interlayer insulating layers on the substrate and has a stepped structure on the second region, an insulating layer on stepped structure of the first stack, a plurality of vertical channel structures provided on the first region to penetrate the first stack, and a separation structure separating the first and second stacks from each other. The insulating layer may include one or more dopants, and a dopant concentration of the insulating layer may decrease as a distance from the substrate increases.