公开(公告)号：US20040171212A1

公开(公告)日：2004-09-02

申请号：US10776053

申请日：2004-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-jun Won ,  Jung-hee Chung ,  Yong-kuk Jeong ,  Se-hoon Oh ,  Dae-jin Kwon ,  Cha-young Yoo

IPC: H01L021/8242 ,  H01L021/20

CPC classification number: H01L21/02068 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/91

Abstract: In a method of manufacturing a capacitor by performing a multi-stepped wet treatment on the surface of a metal electrode, a lower metal electrode of a capacitor is formed, and a primary wet treatment is performed on the surface of the lower metal electrode to remove unwanted surface oxides that may exist on the surface of the lower metal electrode. A secondary wet treatment is then performed on the surface of the lower metal electrode by using a different etchant than the etchant used in the primary wet treatment, in order to remove unwanted surface organic materials that may exist on the surface of the lower metal electrode. A dielectric layer is then formed on the lower metal electrode using a high-k dielectric material. An upper metal electrode is formed on the dielectric layer.

Abstract translation: 在通过对金属电极的表面进行多级湿式处理来制造电容器的方法中，形成电容器的下部金属电极，并对下部金属电极的表面进行一次湿式处理以除去 可能存在于下金属电极表面的不希望的表面氧化物。 然后通过使用与初次湿处理中使用的蚀刻剂不同的蚀刻剂在下金属电极的表面上进行二次湿处理，以便去除可能存在于下金属电极表面上的不希望的表面有机材料。 然后使用高k电介质材料在下金属电极上形成电介质层。 在电介质层上形成上金属电极。

公开(公告)号：US20040009642A1

公开(公告)日：2004-01-15

申请号：US10455676

申请日：2003-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yoon Yoo ,  Moon-han Park ,  Dae-jin Kwon

IPC: H01L021/336 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L27/11568 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02326 ,  H01L21/28282 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/32105 ,  H01L27/115 ,  H01L29/66833

Abstract: In a method of fabricating a non-volatile memory device with a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a silicon nitride layer, which is a charge trapping layer, and a polysilicon layer, which is a control gate electrode, are electrically isolated from one another in the resulting structure. According to the method, a silicon oxide layer as a tunneling layer and a silicon nitride layer pattern as a charge trapping layer are formed on a semiconductor substrate; an oxidation process is performed to form a silicon nitride oxide layer, as a blocking layer, at top and sides of the silicon nitride layer pattern and to form a gate insulating layer at an exposed portion of the semiconductor substrate; and a control gate electrode is formed on the silicon nitride oxide layer and the gate insulating layer.