公开(公告)号：US20040266220A1

公开(公告)日：2004-12-30

申请号：US10900780

申请日：2004-07-28

Applicant: Micron Technology, Inc.

Inventor： Kie Y. Ahn ,  Leonard Forbes

IPC: H01L021/336 ,  H01L021/4763 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L28/82 ,  C23C14/10 ,  C23C14/226 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/02263 ,  H01L21/31695 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predetermined microstructure formed using a glancing angle deposition (GLAD) process. The microstructure includes columnar structures that provide a porous dielectric material. One aspect is a method of forming a low-k insulator structure. In one embodiment, a predetermined vapor flux incidence angle null is set with respect to a normal vector for a substrate surface so as to promote a dielectric microstructure with individual columnar structures. Vapor deposition and substrate motion are coordinated so as to form columnar structures in a predetermined shape. Other aspects are provided herein.

公开(公告)号：US20040266217A1

公开(公告)日：2004-12-30

申请号：US10873256

申请日：2004-06-23

Inventor： Kyoung-seok Kim ,  Hong-bae Park ,  Bong-hyun Kim ,  Sung-tae Kim ,  Jong-wan Kwon ,  Jung-hyun Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Gab-jin Nam ,  Young-sun Kim

IPC: H01L021/8242 ,  H01L021/20 ,  H01L021/469

CPC classification number: H01L21/0228 ,  C23C16/308 ,  C23C16/45531 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02181 ,  H01L21/02205 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/3143 ,  H01L21/31645

Abstract: A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.

Abstract translation: 使用原子层沉积（ALD）形成高电介质膜的方法以及制造具有高电介质膜的电容器的方法包括将含有金属元素的前体供应到半导体衬底并清洗反应器; 供应氧化剂并清洗反应器; 并供应含氮的反应源并清洗反应器。

公开(公告)号：US20040266213A1

公开(公告)日：2004-12-30

申请号：US10880886

申请日：2004-06-30

Inventor： Li Li ,  Pai-Hung Pan

IPC: H01L021/31 ,  H01L021/469 ,  H01L021/336 ,  H01L021/20

CPC classification number: H01L21/28008 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02351 ,  H01L21/26506 ,  H01L21/31662 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/42368 ,  H01L29/66575 ,  Y10S148/116 ,  Y10S148/118

Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

公开(公告)号：US20040251519A1

公开(公告)日：2004-12-16

申请号：US10890263

申请日：2004-07-14

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Gaku Sugahara ,  Yasutoshi Kawaguchi ,  Akihiko Ishibashi ,  Toshiya Yokogawa ,  Atsushi Matsubara

IPC: H01L021/00 ,  H01L021/31 ,  H01L021/469 ,  H01L029/20 ,  H01L031/0304

CPC classification number: H01S5/32341 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/0265 ,  H01S5/0207 ,  H01S5/0213 ,  H01S5/0217 ,  H01S5/1017 ,  H01S5/22 ,  H01S2304/00 ,  H01S2304/12

Abstract: A nitride semiconductor device comprising a substrate (101) having trenches (102b) each formed of a cavity and peaks (102a) formed from a group III nitride on the surface thereof; a nitride semiconductor layer (106) formed on the substrate (101); and a nitride semiconductor multilayered structure that is formed on the nitride semiconductor layer (106) and has an active layer, wherein the lattice constant of the substrate (101) is different from that of the group III nitride substance (102a), the substrate (101) has a mask (104a) formed from a dielectric (104), the mask (104a) is formed only on the side surfaces of the peaks (102a), the upper surfaces of the peaks (102a) are exposed and the substrate (101) is exposed in the trenches (102b), a height L1 of the mask (104a) is not less than 50 nm and not more than 5000 nm, a width L2 of the trench (102b) is not less than 5000 nm and not more than 50000 nm, and an aspect ratio L1/L2 of the trenches (102b) is not less than 0.001 and not more than 1.0. This structure enhances the reliability of the nitride semiconductor devices.

Abstract translation: 一种氮化物半导体器件，包括具有由空腔形成的沟槽（102b）的衬底（101）和在其表面上由III族氮化物形成的峰（102a） 形成在所述基板（101）上的氮化物半导体层（106） 以及氮化物半导体多层结构，其形成在所述氮化物半导体层上并具有活性层，其中，所述基板（101）的晶格常数与所述III族氮化物（102a）的晶格常数不同，所述基板 101）具有由电介质（104）形成的掩模（104a），所述掩模（104a）仅形成在所述峰（102a）的侧表面上，所述峰（102a）的上表面被暴露，并且所述基板 101）暴露在沟槽（102b）中，掩模（104a）的高度L1不小于50nm且不大于5000nm，沟槽（102b）的宽度L2不小于5000nm，而不是 大于50000nm，并且沟槽（102b）的纵横比L1 / L2不小于0.001且不大于1.0。 这种结构提高了氮化物半导体器件的可靠性。

公开(公告)号：US20040248428A1

公开(公告)日：2004-12-09

申请号：US10487731

申请日：2004-02-23

Inventor： Christophe Bureau ,  Edouard Levy ,  Pascal Viel

IPC: H01L021/469

CPC classification number: H01B1/12 ,  B05D5/12 ,  C09D5/4476

Abstract: The present invention relates to a process for grafting and growing a conductive organic film on(to) an electrically conductive or semiconductive surface in which the grafting and growing of the film are performed simultaneously by electro-reduction of a diazonium salt that is a precursor of the said film on(to) the said surface cathodically polarized at a potential greater than or equal, in absolute value, to the electro-reduction potential of the diazonium salt relative to a reference electrode. The invention finds an application especially in the protection of surfaces, the manufacture of localized conductive coatings, of chemical sensors in the fields of chemistry and molecular biology, the manufacture of biomedical equipment, etc.

Abstract translation: 本发明涉及一种用于在导电或半导体表面上接枝和生长导电有机膜的方法，其中通过电还原作为前体的重氮盐同时进行膜的接枝和生长 所述膜以（绝对值）大于或等于绝对值的电位被阴极极化地转换为重氮盐相对于参比电极的电还原电位。 本发明尤其在化学和分子生物学领域的化学传感器的表面保护，局部导电涂层的制造，生物医学设备的制造等方面发现。

公开(公告)号：US20040235312A1

公开(公告)日：2004-11-25

申请号：US10444217

申请日：2003-05-23

Inventor： John D. Loftin ,  Robert D. Clark ,  Arthur Kenneth Hochberg

IPC: H01L021/31 ,  H01L021/469 ,  H01L021/3205 ,  H01L021/4763

CPC classification number: C23C16/45514 ,  C23C16/308 ,  H01L21/3144 ,  H01L21/3145

Abstract: This invention relates to a chemical vapor deposition process for forming Zr or Hf oxynitride films suitable for use in electronic applications such as gate dielectrics. The process comprises: a. delivering a Zr or Hf containing precursor in gaseous form to a chemical vapor deposition chamber; and, b. simultaneously delivering an oxygen source and a nitrogen source to the chamber separately, such that mixing of these sources with the precursor does not take place prior to delivery to the chamber; and, c. contacting the resultant reaction mixture with a substrate in said chamber, said substrate heated to an elevated temperature to effect deposition of the Zr or Hf oxynitride film, respectively. A silicon containing precursor may be added simultaneously to the chamber for forming Zr or Hf silicon oxynitride films.

Abstract translation: 本发明涉及一种用于形成适用于诸如栅极电介质的电子应用中的Zr或Hf氧氮化物膜的化学气相沉积工艺。 该过程包括：a。 将一种含有Zr或Hf的气态前驱体输送到化学气相沉积室; 和，b。 同时将氧源和氮源分别输送到腔室，使得这些源与前体的混合在输送到室之前不发生; 和，c。 使所得反应混合物与所述室中的基材接触，将所述基材加热至高温，分别实施Zr或Hf氧氮化物膜的沉积。 可以将含硅前体同时加入到室中以形成Zr或Hf氮氧化硅膜。

公开(公告)号：US20040229395A1

公开(公告)日：2004-11-18

申请号：US10872746

申请日：2004-06-21

Inventor： Jitendra S. Goela ,  Michael A. Pickering

IPC: H01L021/00 ,  C30B001/00 ,  H01L021/469 ,  H01L021/36

CPC classification number: C23C16/01 ,  C23C16/325

Abstract: An opaque, low resistivity silicon carbide and a method of making the opaque, low resistivity silicon carbide. The opaque, low resistivity silicon carbide is doped with a sufficient amount of nitrogen to provide the desired properties of the silicon carbide. The opaque, low resistivity silicon carbide is a free-standing bulk material that may be machined to form furniture used for holding semi-conductor wafers during processing of the wafers. The opaque, low resistivity silicon carbide is opaque at wavelengths of light where semi-conductor wafers are processed. Such opaqueness provides for improved semi-conductor wafer manufacturing. Edge rings fashioned from the opaque, low resistivity silicon carbide can be employed in RTP chambers.

Abstract translation: 不透明，低电阻率碳化硅和制造不透明低电阻率碳化硅的方法。 不透明的低电阻率碳化硅被掺杂足够量的氮以提供所需的碳化硅性质。 不透明的低电阻率碳化硅是一种独立的散装材料，其可以被机加工以形成用于在晶片加工期间保持半导体晶片的家具。 不透明的低电阻率碳化硅在处理半导体晶片的光的波长处是不透明的。 这种不透明度提供了改进的半导体晶片制造。 由不透明，低电阻率碳化硅形成的边缘环可用于RTP室。

公开(公告)号：US20040227196A1

公开(公告)日：2004-11-18

申请号：US10774522

申请日：2004-02-10

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Kenji Yoneda

IPC: H01L021/469

CPC classification number: H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31111 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/6659

Abstract: Part of a first oxide film formed by thermal oxidation is removed by etching. A second oxide film is formed in the part of substrate from which the first oxide film has been removed using heated nitric acid. The two oxide films are nitrided by a nitrogen plasma having a low energy so as to be first and second gate insulating films, i.e., oxynitride films, respectively.

Abstract translation: 通过蚀刻除去由热氧化形成的第一氧化膜的一部分。 在基板的部分中形成第二氧化物膜，使用加热的硝酸从其去除第一氧化物膜。 两个氧化物膜被具有低能量的氮等离子体氮化，以分别为第一和第二栅极绝缘膜，即氧氮化物膜。

公开(公告)号：US20040224534A1

公开(公告)日：2004-11-11

申请号：US10739901

申请日：2003-12-17

Inventor： Jacobus Johannes Beulens ,  Yuet Mei Wan

IPC: H01L021/469

CPC classification number: H01L21/02329 ,  B82Y10/00 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3185 ,  Y10S977/72

Abstract: A method of forming silicon nitride nanodots that comprises the steps of forming silicon nanodots and then nitriding the silicon nanodots by exposing them to a nitrogen containing gas. Silicon nanodots were formed by low pressure chemical vapor deposition. Nitriding of the silicon nanodots was performed by exposing them to nitrogen radicals formed in a microwave radical generator, using N2 as the source gas.

Abstract translation: 一种形成氮化硅纳米点的方法，其包括以下步骤：形成硅纳米点，然后通过将其暴露于含氮气体来氮化硅纳米点。 通过低压化学气相沉积形成硅纳米点。 通过使用N 2作为源气体将它们暴露于在微波自由基发生器中形成的氮自由基上进行硅纳米点的氮化。

公开(公告)号：US20040224496A1

公开(公告)日：2004-11-11

申请号：US10730193

申请日：2003-12-05

Applicant: Applied Materials, Inc.

Inventor： Zhenjiang Cui ,  Rick J. Roberts ,  Michael S. Cox ,  Jun Zhao

IPC: H01L021/4763 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/76229

Abstract: A method of filling a plurality of trenches etched in a substrate. In one embodiment the method includes depositing a layer of spin-on glass material over the substrate and into the plurality of trenches; exposing the layer of spin-on glass material to a solvent; curing the layer of spin-on glass material; and depositing a layer of silica glass over the cured spin-on glass layer using a chemical vapor deposition technique.