公开(公告)号：US20240072175A1

公开(公告)日：2024-02-29

申请号：US18300579

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhwa Song ,  Changsik Kim ,  Jaewon Na ,  Deokhwan Choi

IPC: H01L29/786 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H01L29/78642 ,  H10B12/315

Abstract: A semiconductor device includes an upper conductive line on a substrate, a channel structure adjacent the upper conductive line, a gate dielectric film between the channel structure and the upper conductive line, and a conductive contact pattern electrically connected to the channel structure. The channel structure includes a main channel portion including an oxide semiconductor layer having a first composition, and a channel contact portion between the main channel portion and the conductive contact pattern. The channel contact portion is in contact with the conductive contact pattern and includes a material having a second composition that is different from the first composition.

公开(公告)号：US20250016991A1

公开(公告)日：2025-01-09

申请号：US18757681

申请日：2024-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaejoon Song ,  Julpin Park ,  Deokhwan Choi

IPC: H10B12/00

Abstract: An integrated circuit memory device (e.g., DRAM) includes a substrate having a bit line thereon, and an electrically insulating region having a first opening therein, which exposes a first portion of the bit line. A first semiconductor active layer is provided, which lines first and second opposing sidewalls of the first opening and the exposed first portion of the bit line, such that a direct electrical connection is provided between the exposed first portion of the bit line and a portion of the first semiconductor active layer extending between the first and second sidewalls of the first opening. A first word line is provided on a first portion of the first semiconductor active layer extending opposite the first sidewall of the first opening, and a second word line is provided on a second portion of the first semiconductor active layer extending opposite the second sidewall of the first opening.

公开(公告)号：US20240172424A1

公开(公告)日：2024-05-23

申请号：US18454206

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhwan Choi ,  Julpin Park ,  In-Jae Bae ,  Dong-Sik Park

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device includes a bit line on a substrate and extending in a first direction, first and second active pillars on the bit line, the first active pillar including a first horizontal portion coupled to the bit line and a first vertical portion extending from the first horizontal portion, the second active pillar including a second horizontal portion coupled to the bit line and a second vertical portion extending from the second horizontal portion. First and second word lines are on the first and second horizontal portions of the first and second active pillars, respectively, and extend in a second direction crossing the first direction. A first insulating layer is between the first and second word lines. A first and second side surfaces of the first and second horizontal portions face each other. The first insulating layer includes an air gap between the first and second side surfaces.