REGION GROWING APPARATUS AND METHOD USING MULTI-CORE
    2.
    发明申请
    REGION GROWING APPARATUS AND METHOD USING MULTI-CORE 有权
    区域生长装置和使用多核的方法

    公开(公告)号:US20130336587A1

    公开(公告)日:2013-12-19

    申请号:US13919384

    申请日:2013-06-17

    CPC classification number: G06T7/0081 G06T7/11 G06T2207/10081

    Abstract: A region growing apparatus using multi-core includes a plurality of cores, each core including an operation controller configured to perform an operation for region growing of a 2D pixel region or 3D pixel region and an inner memory configured to store a queue associated with a seed pixel as a target of the operation; and a shared memory connected to the plurality of cores over a network and shared by the plurality of cores.

    Abstract translation: 使用多核的区域生长装置包括多个核心,每个核心包括被配置为执行2D像素区域或3D像素区域的区域生长的操作的操作控制器和被配置为存储与种子相关联的队列的内部存储器 像素作为操作的目标; 以及通过网络连接到所述多个核并由所述多个核共享的共享存储器。

    DISPLAY APPARATUSES AND METHODS OF OPERATING THE SAME
    3.
    发明申请
    DISPLAY APPARATUSES AND METHODS OF OPERATING THE SAME 审中-公开
    显示装置及其操作方法

    公开(公告)号:US20140071367A1

    公开(公告)日:2014-03-13

    申请号:US14082584

    申请日:2013-11-18

    CPC classification number: G02F1/1368 G09G3/3648 G09G2330/027

    Abstract: Provided are display apparatuses and methods of operating the same. In a display apparatus, a display image may be continuously held for longer than about 10 msec after the power of the display panel is turned off. The display apparatus may indicate a liquid crystal display (LCD) apparatus including an oxide thin film transistor (TFT). Off leakage current of the oxide TFT may be less than about 10−14 A.

    Abstract translation: 提供了显示装置及其操作方法。 在显示装置中,在显示面板的电源关闭之后,显示图像可以连续保持超过约10毫秒。 显示装置可以指示包括氧化物薄膜晶体管(TFT)的液晶显示器(LCD)装置。 氧化物TFT的漏电流可以小于约10-14A。

    SEMICONDUCTOR PACKAGE
    4.
    发明申请

    公开(公告)号:US20230005884A1

    公开(公告)日:2023-01-05

    申请号:US17665810

    申请日:2022-02-07

    Abstract: A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.

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