公开(公告)号：US20210343347A1

公开(公告)日：2021-11-04

申请号：US17375206

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Won Yun ,  Kyung Min Kang ,  Dong Ku Kang

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11556

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

公开(公告)号：US11670377B2

公开(公告)日：2023-06-06

申请号：US17375206

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Won Yun ,  Kyung Min Kang ,  Dong Ku Kang

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

公开(公告)号：US11527473B2

公开(公告)日：2022-12-13

申请号：US17038521

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwa Yun ,  Chan Ho Kim ,  Dong Ku Kang ,  Bong Soon Lim

IPC: H01L23/522 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure disposed on a first substrate, a horizontal semiconductor layer disposed on a second substrate, a plurality of stack structures on the horizontal semiconductor layer in a first direction, wherein the plurality of stack structures include a memory cell region and a capacitor region, a plurality of electrode isolation regions extending in the first direction and a second direction and configured to separate the plurality of stack structures to be connected to the horizontal semiconductor layer and a plurality of through-via structures having a first side connected to a through channel contact through at least one metal pad, wherein a capacitor is formed between each of electrode pads and at least one of electrode isolation regions in the plurality of stack structures or at least one of the plurality of through-via structures.

公开(公告)号：US11114167B2

公开(公告)日：2021-09-07

申请号：US16662247

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Won Yun ,  Kyung Min Kang ,  Dong Ku Kang

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

公开(公告)号：US11563016B2

公开(公告)日：2023-01-24

申请号：US16886898

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwa Yun ,  Chan Ho Kim ,  Dong Ku Kang ,  Bong Soon Lim

IPC: H01L27/11526 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11556 ,  G11C16/08 ,  G11C16/24

Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure on a substrate and including a peripheral circuits, horizontal semiconductor layers on the peripheral logic structure, a stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layers, electrode isolation regions separating the stack structures and extending in the first direction and a second direction, the electrode isolation regions being connected to the horizontal semiconductor layers, and through-via structures in the peripheral logic structure. The through-via structures penetrate the stack structures in the first direction. Each of the through-via structures have one side connected to a corresponding one of the through channel contacts. Capacitors are formed by electrode pads respectively with at least one of the electrode isolation regions or with at least one of the through-via structures.