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公开(公告)号：US11783900B2
公开(公告)日：2023-10-10
申请号：US17840021
申请日：2022-06-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Park , Won Bo Shim , Bong Soon Lim
CPC classification number: G11C16/16 , G11C16/12 , G11C16/24 , G11C16/3445
Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.
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公开(公告)号：US10902922B2
公开(公告)日：2021-01-26
申请号：US16412953
申请日：2019-05-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun Seo , Kui Han Ko , Jin-Young Kim , Il Han Park , Bong Soon Lim
Abstract: A nonvolatile memory includes a first sub-block defined by a first string select line and a first word line; a second sub-block defined by a second string select line different from the first string select line and a second word line different from the first word line; a first vacant block defined by the first string select line and the second word line; and a second vacant block defined by the second string select line and the first word line. First data is programmed in the first sub-block with, second data is programmed in the second sub-block, and no data is programmed in the first vacant block and the second vacant block.
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公开(公告)号：US11527473B2
公开(公告)日：2022-12-13
申请号：US17038521
申请日：2020-09-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwa Yun , Chan Ho Kim , Dong Ku Kang , Bong Soon Lim
IPC: H01L23/522 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure disposed on a first substrate, a horizontal semiconductor layer disposed on a second substrate, a plurality of stack structures on the horizontal semiconductor layer in a first direction, wherein the plurality of stack structures include a memory cell region and a capacitor region, a plurality of electrode isolation regions extending in the first direction and a second direction and configured to separate the plurality of stack structures to be connected to the horizontal semiconductor layer and a plurality of through-via structures having a first side connected to a through channel contact through at least one metal pad, wherein a capacitor is formed between each of electrode pads and at least one of electrode isolation regions in the plurality of stack structures or at least one of the plurality of through-via structures.
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Patent Agency Ranking
公开(公告)号：US11676836B2
公开(公告)日：2023-06-13
申请号：US17536551
申请日：2021-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Ick Son , Dae Seok Byeon , Bong Soon Lim
IPC: H01L21/67 , G11C8/14 , H01L21/66 , H01L23/00 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L27/11573 , G11C7/18 , H01L25/18
CPC classification number: H01L21/67288 , G11C7/18 , G11C8/14 , H01L22/34 , H01L24/05 , H01L24/20 , H01L25/18 , H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L2924/1443
Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.
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公开(公告)号：US11563016B2
公开(公告)日：2023-01-24
申请号：US16886898
申请日：2020-05-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwa Yun , Chan Ho Kim , Dong Ku Kang , Bong Soon Lim
IPC: H01L27/11526 , H01L23/522 , H01L27/11519 , H01L27/11556 , G11C16/08 , G11C16/24
Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure on a substrate and including a peripheral circuits, horizontal semiconductor layers on the peripheral logic structure, a stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layers, electrode isolation regions separating the stack structures and extending in the first direction and a second direction, the electrode isolation regions being connected to the horizontal semiconductor layers, and through-via structures in the peripheral logic structure. The through-via structures penetrate the stack structures in the first direction. Each of the through-via structures have one side connected to a corresponding one of the through channel contacts. Capacitors are formed by electrode pads respectively with at least one of the electrode isolation regions or with at least one of the through-via structures.
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公开(公告)号：US11367487B2
公开(公告)日：2022-06-21
申请号：US16693925
申请日：2019-11-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Park , Won Bo Shim , Bong Soon Lim
Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.
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公开(公告)号：US11201069B2
公开(公告)日：2021-12-14
申请号：US16995093
申请日：2020-08-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Ick Son , Dae Seok Byeon , Bong Soon Lim
IPC: H01L21/67 , H01L21/66 , H01L23/00 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L27/11573 , G11C8/14 , G11C7/18 , H01L25/18
Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.
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公开(公告)号：US11195587B2
公开(公告)日：2021-12-07
申请号：US16886053
申请日：2020-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Ick Son , Dae Seok Byeon , Bong Soon Lim
Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, an input/output circuit, a sensing line, and a detecting circuit. The first semiconductor chip includes bitlines, wordlines, first bonding pads electrically connected to the bitlines, second bonding pads electrically connected to the wordlines, and memory cells electrically connected to the bitlines and the wordlines. The second semiconductor chip includes third bonding pads that are electrically connected to the first bonding pads and fourth bonding pads that are electrically connected to the second bonding pads. The input/output circuit writes data to the memory cells via the third bonding pads. The sensing line extends along edge portions of at least one of the first and second semiconductor chips. The detecting circuit is in the second semiconductor chip and can detect defects from at least one of the first and second semiconductor chips using the sensing line.
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