公开(公告)号：US09087558B2

公开(公告)日：2015-07-21

申请号：US14059619

申请日：2013-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hak Shin ,  Yong-Sang Park ,  Young-Yong Byun ,  In-Chul Jeong

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4099

CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4099

Abstract: A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.

Abstract translation: 半导体器件可以包括第一位线，第二位线，连接到第一位线的存储器单元，位线读出放大器电路和控制电路。 位线读出放大器电路可以耦合到存储单元。 位线读出放大器电路可以包括具有耦合到第一位线的输入节点和耦合到第二位线的输出节点的第一反相器，以及耦合到第二位线的输入节点和输出节点 耦合到第一位线。 控制电路可以被配置为在第一时间段内激活第一逆变器而不启动第二逆变器，并且在第一时间段之后的第二时间段期间同时激活第一逆变器和第二逆变器。

公开(公告)号：US10037817B2

公开(公告)日：2018-07-31

申请号：US14958149

申请日：2015-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Jun Her ,  Dong-Wook Kim ,  Dong-Hak Shin

IPC: G11C29/38 ,  G11C29/44 ,  G11C29/00 ,  G11C29/40 ,  G11C11/401

CPC classification number: G11C29/38 ,  G11C11/401 ,  G11C29/40 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/785

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows; and a data control circuit configured to, sequentially read a first unit of data from N memory cell rows of the plurality of memory cell rows, generate merged test results by comparing bits read from the first units of the N memory cell rows, and output the merged test results, during the test mode of the semiconductor memory device. Therefore, test time for testing the semiconductor memory device may be greatly reduced because a test device may determine pass/fail of the data of the unit of repair unit on one read operation.