公开(公告)号：US09601179B2

公开(公告)日：2017-03-21

申请号：US14723261

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Yong Byun ,  Whi-Young Bae

IPC: G11C7/00 ,  G11C11/406 ,  G11C8/10 ,  G11C11/408 ,  G11C8/04

CPC classification number: G11C11/40618 ,  G11C8/04 ,  G11C8/10 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408

Abstract: A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.

公开(公告)号：US11670559B2

公开(公告)日：2023-06-06

申请号：US17206295

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Choi ,  Jung-Hoon Han ,  Jiho Kim ,  Young-Yong Byun ,  Yeonjin Lee ,  Jihoon Chang

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L23/58 ,  H01L23/29 ,  H01L21/78

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L21/78 ,  H01L23/291 ,  H01L23/296 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/0219 ,  H01L2224/0221 ,  H01L2224/02181 ,  H01L2224/05541 ,  H01L2224/05553

Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

公开(公告)号：US10127102B2

公开(公告)日：2018-11-13

申请号：US15229774

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ye-Sin Ryu ,  Hoi-Ju Chung ,  Sang-Uhn Cha ,  Young-Yong Byun ,  Seong-Jin Jang

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.

公开(公告)号：US09087558B2

公开(公告)日：2015-07-21

申请号：US14059619

申请日：2013-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hak Shin ,  Yong-Sang Park ,  Young-Yong Byun ,  In-Chul Jeong

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4099

CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4099

Abstract: A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.

Abstract translation: 半导体器件可以包括第一位线，第二位线，连接到第一位线的存储器单元，位线读出放大器电路和控制电路。 位线读出放大器电路可以耦合到存储单元。 位线读出放大器电路可以包括具有耦合到第一位线的输入节点和耦合到第二位线的输出节点的第一反相器，以及耦合到第二位线的输入节点和输出节点 耦合到第一位线。 控制电路可以被配置为在第一时间段内激活第一逆变器而不启动第二逆变器，并且在第一时间段之后的第二时间段期间同时激活第一逆变器和第二逆变器。

公开(公告)号：US10062427B2

公开(公告)日：2018-08-28

申请号：US14722634

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Whi-Young Bae ,  Young-Sik Kim ,  Young-Yong Byun

IPC: G06F11/10 ,  G11C11/406 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

CPC classification number: G11C11/406 ,  G06F11/1048 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/24 ,  G11C29/70 ,  G11C29/74 ,  G11C29/783 ,  G11C29/816 ,  G11C2029/0411 ,  G11C2211/4061

Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.

公开(公告)号：US09824946B2

公开(公告)日：2017-11-21

申请号：US15231862

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Yong Byun ,  Ho-Sung Song ,  Chi-Wook Kim

IPC: H01L21/66 ,  H01L21/78 ,  H01L23/544 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/2834 ,  G01R31/2856 ,  G01R31/2884 ,  G01R31/2894 ,  G01R31/31713 ,  G01R31/318511 ,  H01L21/78 ,  H01L22/14 ,  H01L22/32 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.