公开(公告)号：US20180190835A1

公开(公告)日：2018-07-05

申请号：US15911148

申请日：2018-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-hun LEE ,  Dong-won KIM

IPC: H01L29/786 ,  H01L27/11 ,  H01L29/423 ,  H01L29/06 ,  G11C11/419 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/78696 ,  G11C11/419 ,  H01L27/1104 ,  H01L27/11578 ,  H01L27/14616 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66787 ,  H01L29/785

Abstract: A static random access memory (SRAM) device includes a circuit element that includes a first inverter having a first load transistor and a first drive transistor and a second inverter having a second load transistor and a second drive transistor. Input and output nodes of the first inverter and the second inverter are cross-connected to each other. A first transfer transistor is connected to the output node of the first inverter, and a second transfer transistor is connected to the output nodes of the second inverter. Each of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having multi-bridge channels. At least one of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having a different number of multi-bridge channels from the other transistors.

公开(公告)号：US20220216349A1

公开(公告)日：2022-07-07

申请号：US17701930

申请日：2022-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-hun LEE ,  Dong-won KIM

IPC: H01L29/786 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  G11C11/419 ,  H01L27/146 ,  H01L21/02 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

公开(公告)号：US20190097054A1

公开(公告)日：2019-03-28

申请号：US15951385

申请日：2018-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mun-hyeon KIM ,  Sung-man Whang ,  Chang-woo NOH ,  Dong-won KIM ,  Han-su OH

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8232 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/8232 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66795

Abstract: An integrated circuit device includes a base burying insulating film covering a lower side wall of a fin-type active region on a substrate, an isolation pattern having a top surface higher than a top surface of the base burying insulating film, and a gate line covering a channel section of the fin-type active region. The gate line has an upper gate covering an upper portion of the channel section and a lower gate protruding from the upper gate toward the substrate and filling a space between a lower side wall of the channel section and an upper side wall of the isolation pattern.

公开(公告)号：US20190319137A1

公开(公告)日：2019-10-17

申请号：US16453486

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-hun LEE ,  Dong-won KIM

IPC: H01L29/786 ,  H01L27/11 ,  H01L29/06 ,  G11C11/419 ,  H01L27/146 ,  H01L29/423

Abstract: A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

公开(公告)号：US20170162583A1

公开(公告)日：2017-06-08

申请号：US15246526

申请日：2016-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-hun LEE ,  Dong-won KIM

IPC: H01L27/11 ,  G11C11/419 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78696 ,  G11C11/419 ,  H01L27/1104 ,  H01L27/11578 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66787 ,  H01L29/785

Abstract: A static random access memory (SRAM) device includes a circuit element that includes a first inverter having a first load transistor and a first drive transistor and a second inverter having a second load transistor and a second drive transistor. Input and output nodes of the first inverter and the second inverter are cross-connected to each other. A first transfer transistor is connected to the output node of the first inverter, and a second transfer transistor is connected to the output nodes of the second inverter. Each of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having multi-bridge channels. At least one of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having a different number of multi-bridge channels from the other transistors.

公开(公告)号：US20210242201A1

公开(公告)日：2021-08-05

申请号：US17150712

申请日：2021-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-gil KANG ,  Beom-jin PARK ,  Geum-jong BAE ,  Dong-won KIM ,  Jung-gil YANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/308

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.