Abstract:
A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.
Abstract:
A method of controlling a multi-core processor includes allocating at least one core of the multi-core processor to at least one process for execution; generating a translation table with respect to the at least one process to translate a logical ID of the at least one core allocated to the at least one process to a physical ID; and controlling the at least one process based on the translation table generated with respect to the at least one process.
Abstract:
Provided are a rendering method and a rendering apparatus, which perform tile-based rendering. The rendering method includes determining a visible fragment based on a depth test with respect to fragments included in a tile, storing an identifier of a primitive corresponding to the visible fragment, and performing selective rendering on a primitives included in the tile based on the identifier of the primitive. The rendering apparatus implements such a rendering method.
Abstract:
A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.
Abstract:
Provided are apparatuses and methods for rendering. The methods analyze draw commands and graphics states, generate hierarchical graphics states from the graphics states based on a graphics state common to the draw commands, and perform rendering of an image frame based on the hierarchical graphics states. The apparatuses use a hierarchical state generator and a graphics processing unit (GPU) to perform the rendering method.
Abstract:
A method of generating a shader program includes determining a first variable to be used to perform a folding operation that replaces operation formulas included in the shader program by a constant or a second variable, and generating a shader program in which the operation formulas are replaced by the constant or the second variable based on the determined first variable.
Abstract:
A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.
Abstract:
A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.
Abstract:
Provided is a method and apparatus of selecting a preemption technique for a computation unit included in a processor to execute a second task before the at least one computation unit finishes executing a first task. The method includes receiving a preemption request, predicting a cost of preemption techniques based on a progress of the first task until receipt of the preemption request, and selecting one of the preemption techniques based on the predicted cost.
Abstract:
Multiple-thread processing apparatuses and methods are provided. The multiple-thread processing method may include searching for loops in a plurality of threads, calculating a number of repetitions of each of found loops in respective threads among the plurality of threads, determining one or more threads based on the calculated number of repetitions of each of the found loops, dividing at least one of the one or more determined threads into child threads, and processing the child threads separately from one another in the plurality of threads.