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公开(公告)号：US20170277571A1
公开(公告)日：2017-09-28
申请号：US15469828
申请日：2017-03-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Donghoon YOO , Bernhard EGGER
IPC: G06F9/50
Abstract: A method of controlling a multi-core processor includes allocating at least one core of the multi-core processor to at least one process for execution; generating a translation table with respect to the at least one process to translate a logical ID of the at least one core allocated to the at least one process to a physical ID; and controlling the at least one process based on the translation table generated with respect to the at least one process.
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2.发明申请公开(公告)号：US20140149968A1
公开(公告)日：2014-05-29
申请号：US14087667
申请日：2013-11-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Min-Ju LEE , Bernhard EGGER , Jae-jin LEE , Young-Lak KIM , Hong-Gyu KIM , Hong-June KIM
IPC: G06F11/34
CPC classification number: G06F11/3466 , G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/88
Abstract: A dynamic library profiling method and a dynamic library profiling system including writing a first break point instruction at a start address of a dynamic library function, recording a first event count value that is a process performance management unit (PMU) count when a target process executes the first break point instruction, writing a second break point instruction to a return address of the dynamic library function, and calculating a PMU count generated in a processor core while the dynamic library function is executed, by comparing the recorded first event count value with a second event count value that is a process PMU count when the target process executes the second break point instruction, wherein the process PMU count is a cumulative value of PMU counts generated in the processor core while the target process is executed.
Abstract translation: 动态库分析方法和动态库分析系统，包括在动态库函数的起始地址处写入第一中断点指令，当目标进程执行时记录作为过程执行管理单元（PMU）计数的第一事件计数值 第一中断点指令，将第二中断点指令写入到动态库函数的返回地址，以及通过将所记录的第一事件计数值与所述第一事件计数值进行比较来计算在执行所述动态库函数时在处理器核心中生成的PMU计数 第二事件计数值，其是当目标处理执行第二中断点指令时的处理PMU计数，其中处理PMU计数是在执行目标处理时在处理器核心中生成的PMU计数的累积值。
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公开(公告)号：US20240193406A1
公开(公告)日：2024-06-13
申请号：US18501135
申请日：2023-11-03
Inventor： Seok-Young YOON , Bernhard EGGER , Hyemi MIN , Jungyoon KWON , Jaume Mateu CUADRAT
IPC: G06N3/0464
CPC classification number: G06N3/0464
Abstract: A method and apparatus with scheduling a neural network (NN), which relate to extracting and scheduling priorities of operation sets, are provided. A scheduler may be configured to receive a loop structure corresponding to a NN model, generate a plurality of operation sets based on the loop structure, generate a priority table for the operation sets based on memory benefits of the operation sets, and schedule the operation sets based on the priority table.
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4.发明申请公开(公告)号：US20180246554A1
公开(公告)日：2018-08-30
申请号：US15788293
申请日：2017-10-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bernhard EGGER , Younghyun CHO , Su-Rim OH , Dong-hoon YOO
CPC classification number: G06F1/28 , G06F1/206 , G06F1/324 , G06F1/3296
Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.
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公开(公告)号：US20240202527A1
公开(公告)日：2024-06-20
申请号：US18353432
申请日：2023-07-17
Inventor： Seok-Young YOON , Bernhard EGGER , Hyemi MIN , Jaume Mateu CUADRAT
Abstract: A method of processing data is performed by a computing device including processing hardware and storage hardware, the method including: converting, by the processing hardware, a neural network, stored in the storage hardware, from a first neural network format into a second neural network format; obtaining, by the processing hardware, information about hardware configured to perform a neural network operation for the neural network and obtaining partition information; dividing the neural network in the second neural network format into partitions, wherein the dividing is based on the information about the hardware and the partition information, wherein each partition includes a respective layer with an input thereto and an output thereof; optimizing each of the partitions based on a relationship between the input and the output of the corresponding layer; and converting the optimized partitions into the first neural network format.
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Patent Agency Ranking
公开(公告)号：US20240185077A1
公开(公告)日：2024-06-06
申请号：US18320896
申请日：2023-05-19
Inventor： Seok-Young YOON , Bernhard EGGER , Daon PARK , Jungyoon KWON , Hyemi MIN
IPC: G06N3/086
CPC classification number: G06N3/086
Abstract: Apparatuses and methods for drawing a quantization configuration are disclosed, where A method may include generating genes by cataloging possible combinations of a quantization precision and a calibration method for each of layers of a pre-trained neural network, determining layer sensitivity for each of the layers based on combinations corresponding to the genes, determining priorities of the genes and selecting some of the genes based on the respective priority of the genes, generating progeny genes by performing crossover on the selected genes, calculating layer sensitivity for each of the layers corresponding to a combination of the crossover, and updating one or more of the genes using the progeny genes based on a comparison of layer sensitivity of the genes and layer sensitivity of the progeny genes.
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公开(公告)号：US20230195439A1
公开(公告)日：2023-06-22
申请号：US17978528
申请日：2022-11-01
Inventor： Bernhard EGGER , Hyemi MIN
IPC: G06F8/41
CPC classification number: G06F8/452
Abstract: An apparatus includes a processor configured to generate each of intermediate representation codes corresponding to each of a plurality of loop structures obtained that corresponds to a neural network computation based on an input specification file of hardware; schedule instructions included in each of the intermediate representation codes corresponding to the plurality of loop structures; select, based on latency values predicted according to scheduling results of the intermediate representation codes, any one code among the intermediate representation codes; and allocate, based on a scheduling result of the selected intermediate representation code, instructions included in the selected intermediate representation code to resources of the hardware included in the apparatus.
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公开(公告)号：US20210279587A1
公开(公告)日：2021-09-09
申请号：US17190832
申请日：2021-03-03
Applicant: Samsung Electronics Co., Ltd. , SNU R&DB FOUNDATION
Inventor： Bernhard EGGER , Minsu KIM , Hyemi MIN
Abstract: A method and an apparatus for generating a code for a neural network operation are disclosed. The method includes receiving information on hardware configured to perform a neural network operation of the neural network, generating, using a processor, a target mapping model mapping the neural network operation on processing elements available to perform the neural network operation based on the information and a structure of the neural network, and generating a code to configure the hardware to perform the neural network operation based on the target mapping model.
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公开(公告)号：US20180067895A1
公开(公告)日：2018-03-08
申请号：US15697082
申请日：2017-09-06
Inventor： Bernhard EGGER , Ho-chan LEE , Yeon-bok LEE , Suk-jin KIM
CPC classification number: G06F15/7867 , G06F9/30 , G06F9/44505 , G06F12/0646 , G06F13/42 , G06F15/7871 , H03M7/30
Abstract: Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one processing unit used in each of a plurality of cycles, is stored. A plurality of processing units of a reconfigurable processor is divided into a plurality of groups. The configuration data is partitioned into a plurality of pieces of sub-configuration data. Each piece of sub-configuration data corresponding to a respective one of the plurality of groups. If a plurality of adjacent cycles include identical control data, the configuration data is compressed by deleting control data of all but one of the plurality of adjacent cycles, for each sub-configuration data.
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公开(公告)号：US20140075253A1
公开(公告)日：2014-03-13
申请号：US14020061
申请日：2013-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seong-hoon JEONG , Bernhard EGGER , Daeyong SHIN , Changyeon JO
IPC: G06F11/22
CPC classification number: G06F11/2273 , G06F11/263 , G06F2217/68
Abstract: A method for verifying an operation of a reconfigurable processor is provided. The method includes generating an random test program using a test description and an architecture description, executing the generated random test program in a reconfigurable processor and in a simulator, and then comparing type of output values in the execution result.
Abstract translation: 提供了一种用于验证可重构处理器的操作的方法。 该方法包括使用测试描述和架构描述生成随机测试程序，在可重新配置的处理器和模拟器中执行生成的随机测试程序，然后比较执行结果中的输出值的类型。
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