公开(公告)号：US20160253261A1

公开(公告)日：2016-09-01

申请号：US15032867

申请日：2014-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-seok LEE ,  Tai-song JIN

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F11/261 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/3485 ,  G06F17/5022 ,  G06F2201/885 ,  G06F2212/1032

Abstract: Provided method includes storing a first cache snap shot including cache profiling information regarding a cache when a first process being executed by a cycle accurate simulator is terminated; storing a second cache snap shot including the cache profiling information on the cache when a second process is executed in the cycle accurate simulator; comparing the second cache snap shot of the second process and the first cache snap shot of the first process to readjust any one value of a cache hit value and a cache miss value which are present in the second cache snap shot of the second process; and correcting the cache profiling information which is stored in the first cache snap shot of the first process by reflecting the readjusted any one value of the cache hit value and the cache miss value present in the second cache snap shot of the second process.

Abstract translation: 所提供的方法包括当由循环精确模拟器执行的第一处理被终止时，存储包括关于高速缓存的高速缓存分析信息的第一高速缓存快照; 当在所述周期精确模拟器中执行第二处理时，将包括所述高速缓存分析信息的第二高速缓存快照存储在所述高速缓存上; 比较第二进程的第二高速缓存快照和第一进程的第一高速缓存快照，以重新调整存在于第二进程的第二高速缓存快照中的高速缓存命中值和高速缓存未命中值的任何一个值; 以及通过反映重新调整的第二处理的第二高速缓存快照中存在的高速缓存命中值和高速缓存未命中值的任何一个值来校正存储在第一处理的第一高速缓存快照中的缓存分析信息。

公开(公告)号：US20170068620A1

公开(公告)日：2017-03-09

申请号：US15121999

申请日：2015-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Sub KIM ,  Tai-song JIN ,  Do-hyung KIM ,  Seung-won LEE

IPC: G06F12/0844 ,  G06F9/48 ,  G06F13/16 ,  G06F9/52

CPC classification number: G06F12/0844 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/4831 ,  G06F9/52 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/372 ,  G06F13/376 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/281 ,  G06F2212/608

Abstract: A method of preventing a bank conflict in a memory includes determining processing timing of each of threads of function units to access a first memory bank in which occurrence of a bank conflict is expected, setting a variable latency of each of the threads for sequential access of the threads according to the determined processing timing, sequentially storing the threads in a data memory queue according to the determined processing timing, and performing an operation by allowing the threads stored in the data memory queue to sequentially access the first memory bank whenever the variable latency of each of the threads passes.

Abstract translation: 一种防止存储器中的存储体冲突的方法包括：确定功能单元的每个线程的处理定时，以访问预期发生存储体冲突的第一存储体，设置每个线程的可变等待时间以顺序访问 根据所确定的处理定时，线程根据所确定的处理定时顺序地将线程存储在数据存储器队列中，并且通过允许存储在数据存储器队列中的线程在可变延迟时间内顺序地存取第一存储体，执行操作 的每个线程通过。

公开(公告)号：US20150127934A1

公开(公告)日：2015-05-07

申请号：US14461718

申请日：2014-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonseo CHOI ,  Tai-song JIN ,  Donghoon YOO

IPC: G06F9/445

CPC classification number: G06F12/0653 ,  G06F9/30 ,  G06F9/44505 ,  H03M7/30

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract translation: 提供了一种用于优化可重配置处理器的配置存储器的方法和装置。 优化可重配置处理器的配置存储器的方法包括基于可重构处理器的架构和关于配置存储器的信息来分析程序代码的循环的并行性，在每个周期中激活功能单元（FU）的调度组 基于分析的并行度生成循环，生成每个周期的配置数据，以及确定存储器映射以将生成的配置数据存储在配置存储器中。

公开(公告)号：US20160321073A1

公开(公告)日：2016-11-03

申请号：US15100452

申请日：2014-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-un PARK ,  Tai-song JIN ,  Do-hyung KIM ,  Suk-jin KIM

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/3004 ,  G06F9/30098 ,  G06F9/30141 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

Abstract: Provided are a method and an apparatus for controlling a register of a reconfigurable processor. The power of a register may be efficiently used by Obtaining a command for each of a plurality of read ports of the register from a memory, obtaining activation information for each of the plurality of read ports from the obtained command, and determining an address value of each of the plurality of read ports on the basis of the obtained activation information.

Abstract translation: 提供了一种用于控制可重构处理器的寄存器的方法和装置。 通过从存储器获取寄存器的多个读取端口中的每一个的命令，可以有效地使用寄存器的功率，从所获得的命令获得多个读取端口中的每一个的激活信息，并且确定地址值 基于所获得的激活信息，多个读取端口中的每一个。

公开(公告)号：US20150127935A1

公开(公告)日：2015-05-07

申请号：US14461794

申请日：2014-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonseo CHOI ,  Tai-song JIN ,  Donghoon YOO

IPC: G06F9/445

CPC classification number: G06F12/0653 ,  G06F9/30 ,  G06F9/44505 ,  H03M7/30

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

公开(公告)号：US20150127933A1

公开(公告)日：2015-05-07

申请号：US14296876

申请日：2014-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonseo CHOI ,  Tai-song JIN ,  Donghoon YOO

IPC: G06F9/445

CPC classification number: G06F12/0653 ,  G06F9/30 ,  G06F9/44505 ,  H03M7/30

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

公开(公告)号：US20170024216A1

公开(公告)日：2017-01-26

申请号：US15125023

申请日：2015-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-kwan SUH ,  Suk-jin KIM ,  Do-hyung KIM ,  Tai-song JIN

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/50

Abstract: Provided are a method and apparatus for processing a very long instruction word (VLIW) instruction. It is possible to effectively compress code composed of VLIW instructions, by acquiring a calculation allocation instruction including information regarding whether the VLIW instructions are allocated to a plurality of slots; updating a database including the information regarding whether the VLIW instructions are allocated to the plurality of slots based on the acquired calculation allocation instruction; and allocating at least one VLIW instruction to each of the plurality of slots based on the updated database.

Abstract translation: 提供了用于处理非常长的指令字（VLIW）指令的方法和装置。 通过获取包括关于VLIW指令是否被分配给多个时隙的信息的计算分配指令，可以有效地压缩由VLIW指令组成的代码; 基于获取的计算分配指令，更新包括关于是否将VLIW指令分配给多个时隙的信息的数据库; 以及基于更新的数据库将至少一个VLIW指令分配给所述多个时隙中的每一个。

公开(公告)号：US20150127921A1

公开(公告)日：2015-05-07

申请号：US14461831

申请日：2014-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonseo CHOI ,  Tai-song JIN ,  Donghoon YOO

IPC: G06F12/06

CPC classification number: G06F12/0653 ,  G06F9/30 ,  G06F9/44505 ,  H03M7/30

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

公开(公告)号：US20150112662A1

公开(公告)日：2015-04-23

申请号：US14521656

申请日：2014-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tai-song JIN

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/04

Abstract: A method and apparatus for performing a simulation by using a plurality of N processors in parallel include dividing the simulation scenario into N parts to distribute a simulation scenario to each of the processors; performing a high-detail simulation by using a first processor to which a part that includes a beginning part of the divided simulation scenario is distributed, from among the N processors; performing a fast simulation by using each of N−1 processors, other than the first processor; and performing a high-detail simulation based on a snapshot that is generated after the fast simulation is finished, by using each of the N−1 processors.

Abstract translation: 并行地使用多个N个处理器进行模拟的方法和装置包括：将模拟场景划分为N个部分，以将仿真场景分配给每个处理器; 通过使用从所述N个处理器中分出包含所述划分的模拟场景的开始部分的部分的第一处理器来执行高细节模拟; 通过使用除了第一处理器之外的每个N-1处理器执行快速模拟; 并且通过使用N-1个处理器中的每一个，基于快速模拟完成之后生成的快照执行高细节模拟。