中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.026 seconds)

    ACCELERATOR, STORAGE DEVICE, AND VR SYSTEM
    4.
    发明公开
    ACCELERATOR, STORAGE DEVICE, AND VR SYSTEM 审中-公开

    公开(公告)号：US20240007586A1

    公开(公告)日：2024-01-04

    申请号：US18163543

    申请日：2023-02-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sooyoung Ji ,  Minho Kim ,  Dongouk Moon ,  Sanghwa Jin

    IPC: H04N5/265 ,  G06T1/20 ,  G06T11/00 ,  G06T7/13 ,  G06T7/174 ,  G06T1/60

    CPC classification number: H04N5/265 ,  G06T1/20 ,  G06T11/001 ,  G06T7/13 ,  G06T7/174 ,  G06T1/60 ,  G06T2207/20212 ,  G06T2210/52

    Abstract: An accelerator includes a memory access module configured to acquire a plurality of original images for generating a VR image from a input device, and a computing module including a stitching region detector, a stitching processor, an image processor, and a combination processor. The memory access module is configured to transmit the plurality of original images to the stitching region detector. The stitching region detector is configured to detect at least one stitching region and an image region from each of the plurality of original images by performing detection processing on each of the plurality of original images received from the memory access module, to provide the at least one stitching region to the stitching processor, and to provide the image region to the image processor. The stitching processor is configured to generate at least one post-processed stitching region.

    STORAGE DEVICES CONFIGURED TO OBTAIN DATA OF EXTERNAL DEVICES FOR DEBUGGING
    5.
    发明公开
    STORAGE DEVICES CONFIGURED TO OBTAIN DATA OF EXTERNAL DEVICES FOR DEBUGGING 审中-公开

    公开(公告)号：US20230152984A1

    公开(公告)日：2023-05-18

    申请号：US18046478

    申请日：2022-10-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongouk Moon ,  Hyunjoon Yoo

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659

    Abstract: A storage device includes a nonvolatile memory device (NVM) and a storage controller. The NVM includes a first region configured to store user data and a second region not allocated to a user. The storage controller is configured to be connected with a host device through both a first-type bus and a second-type bus different from the first-type bus. The storage controller is configured to receive a first and second request from the host device through the first-type bus. In response to the first request, the storage controller is configured to perform an operation on the NVM. In response to the second request, the storage controller is configured to store first data associated with the storage device in the second region and access the second-type bus to obtain second data of at least one external device obtained by the host device and store the second data in the second region.

    Storage device
    8.
    发明授权
    Storage device 有权

    公开(公告)号：US12153515B2

    公开(公告)日：2024-11-26

    申请号：US18134408

    申请日：2023-04-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sanghwa Jin ,  Dongouk Moon ,  Minho Kim ,  Sooyoung Ji

    IPC: G06F12/00 ,  G06F12/02 ,  G06F13/16

    Abstract: A storage device includes a memory device that stores data, a storage controller that stores a data stream including plural frames in the memory device based on a write request from a host, and a scaler that generates a mapping table in which, for each frame, one or more logical addresses assigned to the frame is mapped to a frame number assigned to the frame. For each frame included in the data stream, the scaler performs an operation of obtaining the one or more logical addresses assigned to the frame by referring to the mapping table and providing a batch read request to the storage controller to read all the one or more logical addresses assigned to the frame. The storage controller controls the memory device to perform a read operation on a memory area corresponding to the one or more logical addresses based on the batch read request.

    Computational storage device, storage system including the same and operation method therefor
    9.
    发明授权
    Computational storage device, storage system including the same and operation method therefor 有权

    公开(公告)号：US12147672B2

    公开(公告)日：2024-11-19

    申请号：US18312817

    申请日：2023-05-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Hwa Jin ,  Min-Ho Kim ,  Dongouk Moon ,  Soo-Young Ji

    IPC: G06F3/06

    Abstract: A computational storage device includes a control module, and a nonvolatile memory connected to the control module. The nonvolatile memory is configured to store a plurality of graph data elements, which comprises a plurality of nodes and a plurality of edges that connect at least a portion of the plurality of nodes to each other, in a first memory area and a second memory area each having a plurality of blocks and having different read speeds. The control module is configured to store a first graph data element of the plurality of graph data elements having a relatively high degree of association with one node of the plurality of nodes in the first memory area, and store a second graph data element of the plurality of graph data elements having a relatively low degree of association with the one node of the plurality of nodes in the second memory area.

    STORAGE DEVICE
    10.
    发明公开
    STORAGE DEVICE 审中-公开

    公开(公告)号：US20230401148A1

    公开(公告)日：2023-12-14

    申请号：US18134408

    申请日：2023-04-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sanghwa Jin ,  Dongouk Moon ,  Minho Kim ,  Sooyoung Ji

    IPC: G06F12/02 ,  G06F13/16

    CPC classification number: G06F12/0246 ,  G06F12/0292 ,  G06F13/1668

    Abstract: A storage device includes a memory device that stores data, a storage controller that stores a data stream including plural frames in the memory device based on a write request from a host, and a scaler that generates a mapping table in which, for each frame, one or more logical addresses assigned to the frame is mapped to a frame number assigned to the frame. For each frame included in the data stream, the scaler performs an operation of obtaining the one or more logical addresses assigned to the frame by referring to the mapping table and providing a batch read request to the storage controller to read all the one or more logical addresses assigned to the frame. The storage controller controls the memory device to perform a read operation on a memory area corresponding to the one or more logical addresses based on the batch read request.

Patent Agency Ranking