公开(公告)号：US20220139954A1

公开(公告)日：2022-05-05

申请号：US17575947

申请日：2022-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon KANG ,  Tae Hun KIM ,  Jae Ryong SIM ,  Kwang Young JUNG ,  Gi Yong CHUNG ,  Jee Hoon HAN ,  Doo Hee HWANG

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US20230154509A1

公开(公告)日：2023-05-18

申请号：US17814640

申请日：2022-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-Hwan CHOO ,  Jun Ha HWANG ,  Doo Hee HWANG

IPC: G11C7/22 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C7/1048 ,  G11C5/14

Abstract: A memory device includes a memory cell for storing data, and a memory controller configured to check whether a dynamic voltage frequency scaling core (DVFSC) operation is used, check information stored in the memory device indicating a setting of the host device in response to the DVFSC operation being used, determine a level of a low voltage used for the DVFSC operation based on the information, and transmit the determined level of the low voltage used for the DVFSC operation to the host device.

公开(公告)号：US20180358374A1

公开(公告)日：2018-12-13

申请号：US15868084

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo KIM ,  Hyun Suk KIM ,  Soon Hyuk HONG ,  Doo Hee HWANG

IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/10 ,  H01L23/532 ,  H01L23/528 ,  H01L27/11565 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L23/53271 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/7926

Abstract: A vertical memory device includes a gate structure including a plurality of gate electrode layers stacked on a substrate, a plurality of channel structures penetrating through the gate structure and extending in a direction perpendicular to an upper surface of the substrate, a common source line penetrating the gate structure and extending in a first direction, a metal line extended above the common source line in the first direction, and a plurality of connection portions interposed between the metal line and the common source line.