公开(公告)号：US09324661B2

公开(公告)日：2016-04-26

申请号：US14673852

申请日：2015-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Jin Kim ,  Young-Sik Kim ,  Tea-Seog Um ,  Yong-Dae Ha

IPC: H01L23/544 ,  H01L23/52 ,  H01L25/07 ,  H01L25/00 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01L23/544 ,  H01L21/67144 ,  H01L21/6836 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An aligning guide, a semiconductor package comprising an aligning guide, and a method of manufacturing a semiconductor package comprising an aligning guide are provided. The semiconductor package may comprise a circuit board and an aligning guide mounted on the circuit board. The aligning guide may have a plurality of stepped portions. A plurality of semiconductor chips may be stacked on the circuit board and engage with the stepped portions of the aligning guide. According to the disclosed semiconductor package, a large number of semiconductor chips may be stacked with high accuracy and sufficient margin. Therefore, the rate of failure and defects in the chip stacking process may be reduced and the reliability and stability of the semiconductor package may be enhanced.

Abstract translation: 提供了一种对准引导件，包括对准引导件的半导体封装以及包括对准引导件的半导体封装的制造方法。 半导体封装可以包括安装在电路板上的电路板和对准引导件。 对准引导件可以具有多个阶梯部分。 多个半导体芯片可以堆叠在电路板上并与对准引导件的阶梯部分接合。 根据所公开的半导体封装，可以以高精度和足够的余量堆叠大量的半导体芯片。 因此，可以降低芯片堆叠过程中的故障率和缺陷，并且可以提高半导体封装的可靠性和稳定性。