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公开(公告)号：US12192320B2
公开(公告)日：2025-01-07
申请号：US17218790
申请日：2021-03-31
Applicant: Samsung Electronics Co., Ltd , SNU R&DB FOUNDATION , Industry-Academic Cooperation Foundation, Chosun University
Inventor： Jong-Seon No , Joonwoo Lee , Young-Sik Kim , Yongwoo Lee , Eunsang Lee
IPC: H04L9/00
Abstract: Disclosed is an encryption method and apparatus. The encryption method using homomorphic encryption may include generating a ciphertext by encrypting data, and bootstrapping the ciphertext by performing a modular reduction based on a selection of one or more target points for a modulus corresponding to the ciphertext.
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公开(公告)号：US10666467B2
公开(公告)日：2020-05-26
申请号：US16108894
申请日：2018-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hye Jung Kwon , Seungjun Bae , Yongjae Lee , Young-Sik Kim , Young-Ju Kim , Suyeon Doo , Yoon-Joo Eom
Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.
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3.发明授权Concentrated address detecting method of semiconductor device and concentrated address detecting circuit using the same 有权半导体器件的集中地址检测方法及使用其的集中地址检测电路公开(公告)号：US09171605B1
公开(公告)日：2015-10-27
申请号：US14103794
申请日：2013-12-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Young-Sik Kim , Won-Il Bae , Myeong-O Kim , Min-Soo Kim , Ho-Seok Seol , Min-Sang Park , Kyo-Min Sohn , Chi-Hwan Lee , Sang-Joon Hwang
IPC: G11C11/408 , G11C11/406
CPC classification number: G11C11/40607 , G06F12/1018 , G11C7/00 , G11C11/402 , G11C11/406 , G11C11/40615 , G11C11/408
Abstract: Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.
Abstract translation: 提供了使用n位地址来检测半导体器件的集中地址的方法。 该方法包括：对于k组中的每一组，将n位地址划分为k个组，其中n和k中的每一个是等于或大于2的整数，检测对应于该组的一个或多个集中子地址，以及 通过组合用于k个组的一个或多个集中子地址来生成至少一个集中地址。
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4.发明授权公开(公告)号：US11671239B2
公开(公告)日：2023-06-06
申请号：US17192162
申请日：2021-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD. , SNU R&DB FOUNDATION , Industry-Academic Cooperation Foundation, Chosun University
Inventor： Jung-Seon No , Joonwoo Lee , Young-Sik Kim , Youngwoo Lee , Eunsang Lee
IPC: H04L9/00
CPC classification number: H04L9/008
Abstract: An encryption method and apparatus based on homomorphic encryption using an odd function property. The encryption method includes generating a ciphertext by encrypting data, and bootstrapping the ciphertext by performing a modular reduction based on an odd function property for a modulus corresponding to the ciphertext.
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公开(公告)号：US09324661B2
公开(公告)日：2016-04-26
申请号：US14673852
申请日：2015-03-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Doo-Jin Kim , Young-Sik Kim , Tea-Seog Um , Yong-Dae Ha
IPC: H01L23/544 , H01L23/52 , H01L25/07 , H01L25/00 , H01L21/67 , H01L21/683
CPC classification number: H01L23/544 , H01L21/67144 , H01L21/6836 , H01L25/074 , H01L25/50 , H01L2221/68354 , H01L2221/68381 , H01L2223/54426 , H01L2223/54486 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/73265 , H01L2225/06562 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: An aligning guide, a semiconductor package comprising an aligning guide, and a method of manufacturing a semiconductor package comprising an aligning guide are provided. The semiconductor package may comprise a circuit board and an aligning guide mounted on the circuit board. The aligning guide may have a plurality of stepped portions. A plurality of semiconductor chips may be stacked on the circuit board and engage with the stepped portions of the aligning guide. According to the disclosed semiconductor package, a large number of semiconductor chips may be stacked with high accuracy and sufficient margin. Therefore, the rate of failure and defects in the chip stacking process may be reduced and the reliability and stability of the semiconductor package may be enhanced.
Abstract translation: 提供了一种对准引导件，包括对准引导件的半导体封装以及包括对准引导件的半导体封装的制造方法。 半导体封装可以包括安装在电路板上的电路板和对准引导件。 对准引导件可以具有多个阶梯部分。 多个半导体芯片可以堆叠在电路板上并与对准引导件的阶梯部分接合。 根据所公开的半导体封装，可以以高精度和足够的余量堆叠大量的半导体芯片。 因此，可以降低芯片堆叠过程中的故障率和缺陷，并且可以提高半导体封装的可靠性和稳定性。
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Patent Agency Ranking
公开(公告)号：US12231544B2
公开(公告)日：2025-02-18
申请号：US18521187
申请日：2023-11-28
Applicant: Samsung Electronics Co., Ltd. , Seoul National University R&DB Foundation , Industry Academic Cooperation Foundation, Chosun University
Inventor： Jong-Seon No , Yongwoo Lee , Young-Sik Kim
Abstract: A processor-implemented method with homomorphic encryption includes: receiving a first ciphertext corresponding to a first modulus; generating a second ciphertext corresponding to a second modulus by performing modulus raising on the first ciphertext; and performing bootstrapping by encoding the second ciphertext using a commutative property and an associative property of operations included in a rotation operation.
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公开(公告)号：US11870889B2
公开(公告)日：2024-01-09
申请号：US17516924
申请日：2021-11-02
Applicant: Samsung Electronics Co., Ltd. , Seoul National University R&DB Foundation , Industry Academic Cooperation Foundation, Chosun University
Inventor： Jong-Seon No , Yongwoo Lee , Young-Sik Kim
CPC classification number: H04L9/0825 , G06F7/523 , G06F7/766 , G06F17/16 , H04L9/008 , H04L9/0618
Abstract: A processor-implemented method with homomorphic encryption includes: receiving a first ciphertext corresponding to a first modulus; generating a second ciphertext corresponding to a second modulus by performing modulus raising on the first ciphertext; and performing bootstrapping by encoding the second ciphertext using a commutative property and an associative property of operations included in a rotation operation.
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公开(公告)号：US11438016B2
公开(公告)日：2022-09-06
申请号：US17110777
申请日：2020-12-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Uhn Cha , Ye-Sin Ryu , Young-Sik Kim , Su-Yeon Doo
Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
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公开(公告)号：US11307918B2
公开(公告)日：2022-04-19
申请号：US16594400
申请日：2019-10-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun chu Oh , Young-Sik Kim , Hee-hyun Nam , Young-geun Lee , Young-jin Cho
IPC: G06F11/07 , G06F11/14 , G06F11/34 , G11C11/409 , G11C11/408 , G06F13/16 , G11C29/52 , G11C11/16 , G11C13/00 , G11C29/04
Abstract: A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells.
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公开(公告)号：US11223373B2
公开(公告)日：2022-01-11
申请号：US16599648
申请日：2019-10-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Uhn Cha , Ye-Sin Ryu , Young-Sik Kim , Su-Yeon Doo
Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
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