公开(公告)号：US20220278011A1

公开(公告)日：2022-09-01

申请号：US17749825

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghawn BAE ,  Doohwan LEE ,  Jooyoung CHOI

IPC: H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L23/367

Abstract: Provided is method of manufacturing a semiconductor device. The method includes: forming a metal layer on a carrier; forming a conductor pattern layer on the metal layer; mounting a semiconductor chip on a tape; forming an encapsulant covering the semiconductor chip; attaching the conductor pattern layer to the encapsulant; removing the tape; and forming a connection structure electrically connected to the semiconductor chip in an area from which the tape is removed.

公开(公告)号：US20210407962A1

公开(公告)日：2021-12-30

申请号：US17154789

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongwon KIM ,  Junmo KOO ,  Yeonjoo KIM ,  Yunhee KIM ,  Jongkook KIM ,  Doohwan LEE ,  Jeongho LEE

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a base substrate, an interposer package disposed on the base substrate, and first and second semiconductor chips disposed on the interposer package, the interposer package includes a first redistribution layer, a bridge chip including a bridge circuit, and a vertical connection structure including a plurality of wiring layers, and wherein each of the first semiconductor chip and the second semiconductor chip is electrically connected to the bridge circuit and the plurality of wiring layers through the first redistribution layer.

公开(公告)号：US20210407924A1

公开(公告)日：2021-12-30

申请号：US17306555

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Doohwan LEE

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.

公开(公告)号：US20240145397A1

公开(公告)日：2024-05-02

申请号：US18403583

申请日：2024-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Doohwan LEE

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/18 ,  H01L2221/68372 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161

Abstract: A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.

公开(公告)号：US20210384991A1

公开(公告)日：2021-12-09

申请号：US17285943

申请日：2019-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongil YANG ,  Seonjun KIM ,  Jonghyun PARK ,  Doohwan LEE ,  Jongin LEE

IPC: H04B17/17 ,  H04B17/318

Abstract: Disclosed is an antenna module, which include a first antenna element, a second antenna element, and a communication module that includes a first transmit path and a first receive path connected with the first antenna element, a second transmit path and a second receive path connected with the second antenna element, and a detection circuit connected with at least a part of the second receive path. The communication module may output a specified signal by using the first transmit path and the first antenna element based at least on obtaining a request for identifying a state of the antenna module from an external device, may obtain the output specified signal by using the second receive path and the second antenna element, may identify an intensity of the obtained specified signal by using the detection circuit, and may determine whether the antenna module is abnormal, based at least on the intensity of the obtained specified signal. Moreover, various embodiment found through the present disclosure are possible.

公开(公告)号：US20220230912A1

公开(公告)日：2022-07-21

申请号：US17714546

申请日：2022-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dowan KIM ,  Doohwan LEE ,  Seunghwan BAEK

IPC: H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.

公开(公告)号：US20220209810A1

公开(公告)日：2022-06-30

申请号：US17562333

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yousung LEE ,  Dongil YANG ,  Hyoseok NA ,  Doohwan LEE

IPC: H04B1/44 ,  H03F3/24

Abstract: The disclosure relates to an electronic device and a method for wireless communication including a power amplification circuit. According to an embodiment, an electronic device may include: a radio frequency processing module comprising radio frequency circuitry, a first power amplification circuit connected to the radio frequency processing module, a second power amplification circuit connected to the radio frequency processing module and the first power amplification circuit, and a front-end module comprising circuitry connected to the second power amplification circuit and an antenna and configured to transmit a signal, wherein the second power amplification circuit is configured to acquire, from the first power amplification circuit, a first signal obtained by amplifying a signal output from the radio frequency processing module and a second signal by amplifying a signal output from the radio frequency processing module, based on a combination of frequency bands for a first communication scheme and a second communication scheme, and switch at least one of the first signal or the second signal to at least one output port connected to the front-end module, based on a first frequency band of the first signal and a second frequency band of the second signal. Other embodiments are also possible.

公开(公告)号：US20200152535A1

公开(公告)日：2020-05-14

申请号：US16672652

申请日：2019-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghawn BAE ,  Doohwan LEE ,  Jooyoung CHOI

IPC: H01L23/31 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

Abstract: The invention provides a semiconductor package, which may include a connection structure including one or more redistribution layers. A semiconductor chip is disposed on the connection structure and has an active surface on which a connection pad electrically connected to the redistribution layer is disposed and an inactive surface opposite to the active surface. An encapsulant is disposed on the connection structure and covers at least a portion of the inactive surface of the semiconductor chip. A conductor pattern layer is embedded in the encapsulant such that one exposed surface of the conductor pattern layer is exposed from the encapsulant. A metal layer is disposed on the encapsulant and covers the one exposed surface of the conductor pattern layer.

公开(公告)号：US20230136122A1

公开(公告)日：2023-05-04

申请号：US18077882

申请日：2022-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongil YANG ,  Taeyoung KIM ,  Hyoseok NA ,  Jonghyun PARK ,  Doohwan LEE

IPC: H01H9/54 ,  H01H9/02

Abstract: A switch in an electronic device includes a substrate, a first signal line, a second signal line, and a ground bridge. The first signal line is on the substrate and extends in a first direction. The second signal line is on the substrate and is spaced apart from the first signal line in a first direction parallel with the first signal line to branch the wireless communication signal at a first point and a second point of the first signal line. The ground bridge is at least partially movable in a space between the first signal line and the second signal line. A first capacitor is between a first point of the first signal line and one end of the second signal line, and a second capacitor is between a second point of the first signal line and the other end of the second signal line.

公开(公告)号：US20230060618A1

公开(公告)日：2023-03-02

申请号：US17752083

申请日：2022-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongho LEE ,  Doohwan LEE

IPC: H01L23/498 ,  H01L25/10 ,  H01L21/48

Abstract: A semiconductor package includes a redistribution portion including an insulating layer, a redistribution layer, and a redistribution via, an under-bump metallurgy (UBM) layer below the redistribution portion and including a UBM pad on a lower surface of the redistribution portion and a UBM via on the UBM pad to penetrate through the insulating layer, a semiconductor chip on an upper surface of the redistribution portion and electrically connected to the redistribution layer, an adhesive layer between the UBM layer and the insulating layer and including a conductive material, and a connection bump below the UBM pad and connected to the UBM layer. The UBM pad has a first diameter, and the UBM via has a second diameter, less than the first diameter, and an upper surface of the UBM pad is located on the same level as, or a level lower than, a lower surface of the insulating layer.