Three-dimensional semiconductor device having a peripheral connection plug in a through region below a gate stack structure

    公开(公告)号:US10777571B2

    公开(公告)日:2020-09-15

    申请号:US16137079

    申请日:2018-09-20

    Abstract: A three-dimensional semiconductor device including: a peripheral circuit structure disposed between first and second substrates and including a plurality of peripheral interconnections; a gate-stack structure disposed on the second substrate and including a plurality of gate electrodes stacked and spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, wherein the plurality of gate electrodes include a lower gate electrode, a plurality of intermediate gate electrodes disposed on the lower gate electrode, and an upper gate electrode disposed on the plurality of intermediate gate electrodes; a first through region passing through the second substrate and disposed below the gate-stack structure; a second through region passing through the second substrate and the gate-stack structure; and a first peripheral connection plug passing through the first through region and electrically connecting the lower gate electrode to a first peripheral interconnection of the peripheral interconnections.

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