公开(公告)号：US20200013715A1

公开(公告)日：2020-01-09

申请号：US16385188

申请日：2019-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hwan Park ,  Seong Ho Park ,  Kyoung Pil Park ,  Tae Yong Bae ,  Eun-Chul Seo

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a first wiring and a second wiring disposed at a first metal level, a third wiring and a fourth wiring disposed at a second metal level different from the first metal level, a first via which directly connects the first wiring and the third wiring, a fifth wiring disposed at a third metal level between the first metal level and the second metal level and connected to the second wiring, and a second via which directly connects the fourth wiring and the fifth wiring.

公开(公告)号：US11075160B2

公开(公告)日：2021-07-27

申请号：US16385188

申请日：2019-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hwan Park ,  Seong Ho Park ,  Kyoung Pil Park ,  Tae Yong Bae ,  Eun-Chul Seo

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a first wiring and a second wiring disposed at a first metal level, a third wiring and a fourth wiring disposed at a second metal level different from the first metal level, a first via which directly connects the first wiring and the third wiring, a fifth wiring disposed at a third metal level between the first metal level and the second metal level and connected to the second wiring, and a second via which directly connects the fourth wiring and the fifth wiring.

公开(公告)号：US10923402B2

公开(公告)日：2021-02-16

申请号：US16358810

申请日：2019-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Chul Seo ,  Kyoungpil Park ,  Doo-Hwan Park ,  Seongho Park ,  Aee Young Park ,  Kyungmin Chung

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/308 ,  H01L27/092 ,  H01L21/768 ,  H01L21/56 ,  H01L21/033

Abstract: A method of manufacturing a semiconductor device may include forming a hardmask layer on a substrate, forming a first mold pattern on the hardmask layer using a first photolithography process, conformally forming a spacer layer on the first mold pattern and on portions of the hardmask layer exposed by the first mold pattern, forming a first mold layer using a second photolithography process. The first mold layer may have a first opening that exposes a portion of the spacer layer. The method may include forming a spacer pattern by anisotropically etching the portion of the spacer layer exposed by the first opening until a portion of a top surface of the hardmask layer is exposed, and using the spacer pattern as an etching mask to pattern the hardmask layer.