公开(公告)号：US20250006641A1

公开(公告)日：2025-01-02

申请号：US18405023

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Hee KANG ,  Jong Min BAEK ,  Eui Bok LEE

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device including a first interlayer insulating layer on a substrate, a lower wiring pattern in the first interlayer insulating layer, a second interlayer insulating layer on the first interlayer insulating layer, a via filling layer filling a via trench in the second interlayer insulating layer, a third interlayer insulating layer contacting an upper surface of the second interlayer insulating layer, and an upper wiring pattern in an upper wiring trench formed on the via trench in the third interlayer insulating layer and contacting an upper surface of the via filling layer, the upper wiring pattern including a first upper wiring barrier layer on sidewalls of the upper wiring trench, a second upper wiring barrier layer on sidewalls of the first upper wiring barrier layer and the upper surface of the via filling layer, and an upper wiring filling layer on the second upper wiring barrier layer.

公开(公告)号：US20190043803A1

公开(公告)日：2019-02-07

申请号：US15840128

申请日：2017-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung YOU ,  Eui Bok LEE ,  Jong Min BAEK ,  Su Hyun BARK ,  Jang Ho LEE ,  Sang Hoon AHN ,  Hyeok Sang OH

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.

公开(公告)号：US20240120274A1

公开(公告)日：2024-04-11

申请号：US18217012

申请日：2023-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Rak Hwan KIM ,  Jong Min BAEK ,  Moon Kyun SONG

IPC: H01L23/522 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/088

Abstract: A semiconductor device a first fin-shaped pattern provided at a first surface of a substrate and extending in a second direction, a first source/drain pattern disposed on the first fin-shaped pattern and connected thereto, a first source/drain contact disposed on the first source/drain pattern and connected thereto, a buried conductive pattern extending through the substrate and connected to the first source/drain contact, a contact connection via disposed between the first source/drain contact and the buried conductive pattern. The contact connection via is directly connected to the first source/drain contact and a back wiring line disposed on a second surface of the substrate and connected to the buried conductive pattern. A width of the contact connection via increases as the contact connection via extends away from the second surface. A width of the first source/drain contact decreases as the first source/drain contact extends away from the second surface of the substrate.

公开(公告)号：US20220199522A1

公开(公告)日：2022-06-23

申请号：US17373573

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Donggon YOO ,  Wandon KIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/06

Abstract: A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.

公开(公告)号：US20240222453A1

公开(公告)日：2024-07-04

申请号：US18228376

申请日：2023-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eui Bok LEE ,  Rak Hwan KIM ,  Jong Min BAEK ,  Moon Kyun SONG

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775

CPC classification number: H01L29/41766 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/775

Abstract: A semiconductor device includes an interlayer insulating film including a first surface and a second surface opposite to the first surface in a first direction; a source/drain pattern provided in the interlayer insulating film; a channel pattern adjacent to the source/drain pattern in a second direction and contacting the source/drain pattern; a front wiring provided on the first surface of the interlayer insulating film; a back wiring provided on the second surface of the interlayer insulating film; and a first connecting via contact and a second connecting via contact which are provided between the source/drain pattern and the back wiring and connected to the source/drain pattern.

公开(公告)号：US20230253310A1

公开(公告)日：2023-08-10

申请号：US18299926

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Donggon Yoo ,  Wandon Kim

IPC: H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L29/0649 ,  H01L29/0847 ,  H01L23/5283

Abstract: A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.

公开(公告)号：US20240222450A1

公开(公告)日：2024-07-04

申请号：US18221479

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Moon Kyun SONG

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a fin-shaped pattern, a field insulating film covering a sidewall of the fin-shaped pattern, a source/drain pattern disposed on an upper surface of the fin-shaped pattern, a source/drain etch stop film extending along an upper surface of the field insulating film and a sidewall of the source/drain pattern, a source/drain contact connected to the source/drain pattern, a buried conductive pattern penetrating through a substrate and connected to the source/drain contact, a portion of the buried conductive pattern being disposed within the field insulating film, and a rear wiring line connected to the buried conductive pattern. The field insulating film includes a first field filling film and a first field stop film. The first field stop film is disposed between the first field filling film and the substrate. The first field stop film includes a material having etch selectivity with respect to the first field filling film.

公开(公告)号：US20190148289A1

公开(公告)日：2019-05-16

申请号：US15987211

申请日：2018-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Seok SEO ,  Jong Min BAEK ,  Su Hyun BARK ,  Sang Hoon AHN ,  Hyeok Sang OH ,  Eui Bok LEE

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.

公开(公告)号：US20230282512A1

公开(公告)日：2023-09-07

申请号：US17991090

申请日：2022-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Wook KIM ,  Seung Yong YOO ,  Eui Bok LEE ,  Jin Nam KIM ,  Eun-Ji JUNG

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76844 ,  H01L23/535 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895

Abstract: A semiconductor device is provided. The semiconductor device includes: a lower line structure; an upper interlayer insulating film provided on the lower line structure and having a trench formed therein, wherein the trench includes a wiring line trench and a via trench extending from the wiring line trench to the lower line structure; and an upper line structure provided in the line trench, wherein the upper line structure includes an upper barrier film and an upper filling film. The upper filling film includes a first sub-filling film in contact with the upper interlayer insulating film, and a second sub-filling film provided on the first sub-filling film. The first sub-filling film fills an entirety of the upper via trench and covers at least a portion of a bottom surface of the upper wiring line trench.

公开(公告)号：US20190304903A1

公开(公告)日：2019-10-03

申请号：US16446226

申请日：2019-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung YOU ,  Eui Bok LEE ,  Jong Min BAEK ,  Su Hyun BARK ,  Jang Ho LEE ,  Sang Hoon AHN ,  Hyeok Sang OH

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.