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公开(公告)号：US11257531B2
公开(公告)日：2022-02-22
申请号：US17159516
申请日：2021-01-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-june Park , Jeong-don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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公开(公告)号：US20210151089A1
公开(公告)日：2021-05-20
申请号：US17159516
申请日：2021-01-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-june Park , Jeong-don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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Patent Agency Ranking
公开(公告)号：US10937474B2
公开(公告)日：2021-03-02
申请号：US16668685
申请日：2019-10-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-june Park , Jeong-don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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公开(公告)号：US09635078B2
公开(公告)日：2017-04-25
申请号：US14278693
申请日：2014-05-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-chool Lee , Eun-ji Kim , Min-gon Shin
IPC: G06F15/16 , H04L29/06 , H04N21/239 , H04N21/437 , H04N21/6437
CPC classification number: H04L65/4084 , H04L65/4092 , H04L65/608 , H04N21/2393 , H04N21/437 , H04N21/6437
Abstract: A server, a user terminal apparatus, and a method for providing a streaming data service are disclosed. The method of providing streaming data to a user terminal apparatus from a server includes receiving a describe message from the user terminal apparatus via a real-time stream protocol scheme, transmitting a response message containing content execution information about at least one content of a streaming data service and content list information pre-stored in relation to at least one content stored in a storage medium to the user terminal apparatus when the describe message is received, and transmitting streaming data about content of the streaming data service or content stored in the storage medium to the user terminal apparatus when streaming data service request is received from the user terminal apparatus based on the response message.
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5.发明申请公开(公告)号：US20200066317A1
公开(公告)日：2020-02-27
申请号：US16668685
申请日：2019-10-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-june Park , Jeong-don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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公开(公告)号：US10482935B2
公开(公告)日：2019-11-19
申请号：US15982431
申请日：2018-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-june Park , Jeong-Don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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7.发明申请公开(公告)号：US20180350414A1
公开(公告)日：2018-12-06
申请号：US15982431
申请日：2018-05-17
Applicant: Samsung Electronics Co, Ltd
Inventor： Jung-june PARK , Jeong-Don Ihm , Byung-hoon Jeong , Eun-ji Kim , Ji-yeon Shin , Young-don Choi
CPC classification number: G11C7/222 , G11C7/1057 , G11C7/1066 , G11C16/26 , G11C16/32 , G11C2207/2254 , H03K3/017 , H03K5/1565
Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
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