公开(公告)号：US20240178274A1

公开(公告)日：2024-05-30

申请号：US18366922

申请日：2023-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gunho Jo ,  Heesub Kim ,  Seung Hyun Lim ,  Bomi Kim ,  Eunho Cho

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775

Abstract: An integrated circuit device includes a first fin-type active region and a second fin-type active region, a device isolation film adjacent to each of the first and second fin-type active regions, a first gate line on the first fin-type active region, a second gate line on the second fin-type active region, and a gate cut insulating pattern separating the first and second gate lines, wherein the device isolation film includes a first local isolation portion and a second local isolation portion, which are separating the first fin-type active region from the second fin-type active region to be apart from each other with the gate cut insulating pattern therebetween.

公开(公告)号：US20240379550A1

公开(公告)日：2024-11-14

申请号：US18641698

申请日：2024-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heeseop Kim ,  Gunho Jo ,  Bomi Kim ,  Eunho Cho

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate having an active region extending in a first direction, a gate structure on the active region, intersecting the active region and extending in a second direction, a source/drain region adjacent the gate structure and on the active region, a contact plug on the source/drain region and electrically connected to the source/drain regions, a first power structure on one side of the source/drain region in the second direction and electrically connected to the contact plug, and a second power structure penetrating the substrate and on a lower end of the first power structure. The first power structure and the second power structure are integrated as a unitary structure, and the first power structure has a first width at an upper thereof and a second width at the lower end thereof, the second width being equal to or greater than the first width.

公开(公告)号：US20240274677A1

公开(公告)日：2024-08-15

申请号：US18370249

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gunho Jo ,  Chulsung Kim ,  Bomi Kim ,  Heesub Kim ,  Eunho Cho

IPC: H01L29/417 ,  H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes fin-type active regions protruding from a substrate and extending lengthwise in a first horizontal direction, source/drain regions respectively arranged on the fin-type active regions, a device isolation film covering both sidewalls of each fin-type active region, an insulating structure covering the source/drain regions and the device isolation film, source/drain contacts respectively arranged on and connected to the source/drain regions and apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and a contact isolation insulating film arranged between the source/drain contacts in the second horizontal direction and having a lower surface closer to the substrate than a lower surface of each source/drain contact. At least one of the source/drain contacts includes a first portion extending in a vertical direction toward the substrate along a surface of the contact isolation insulating film.

公开(公告)号：US20240170483A1

公开(公告)日：2024-05-23

申请号：US18347919

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gunho Jo ,  Heesub Kim ,  Seung Hyun Lim ,  Bomi Kim ,  Eunho Cho

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L23/5286

Abstract: An integrated circuit device includes a fin-type active region including a first fin portion and a second fin portion apart from each other in a first lateral direction with a contact space therebetween, a first source/drain region on the fin-type active region at a position overlapping the contact space in a vertical direction, a gate line on the first fin portion, a device isolation film covering both sidewalls of each of the first and second fin portions and defining a width of the contact space, a back side source/drain contact electrically connected to the first source/drain region, filling the contact space, and having a sidewall facing each of the first and second fin portions and the device isolation film, and an etch stop layer contacting a top surface of each of the first and second fin portions between the first fin portion and the gate line.