INTEGRATED CIRCUIT DEVICE
    3.
    发明公开

    公开(公告)号:US20240274677A1

    公开(公告)日:2024-08-15

    申请号:US18370249

    申请日:2023-09-19

    Abstract: An integrated circuit device includes fin-type active regions protruding from a substrate and extending lengthwise in a first horizontal direction, source/drain regions respectively arranged on the fin-type active regions, a device isolation film covering both sidewalls of each fin-type active region, an insulating structure covering the source/drain regions and the device isolation film, source/drain contacts respectively arranged on and connected to the source/drain regions and apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and a contact isolation insulating film arranged between the source/drain contacts in the second horizontal direction and having a lower surface closer to the substrate than a lower surface of each source/drain contact. At least one of the source/drain contacts includes a first portion extending in a vertical direction toward the substrate along a surface of the contact isolation insulating film.

    INTEGRATED CIRCUIT DEVICE
    4.
    发明公开

    公开(公告)号:US20240170483A1

    公开(公告)日:2024-05-23

    申请号:US18347919

    申请日:2023-07-06

    CPC classification number: H01L27/088 H01L21/823475 H01L23/5286

    Abstract: An integrated circuit device includes a fin-type active region including a first fin portion and a second fin portion apart from each other in a first lateral direction with a contact space therebetween, a first source/drain region on the fin-type active region at a position overlapping the contact space in a vertical direction, a gate line on the first fin portion, a device isolation film covering both sidewalls of each of the first and second fin portions and defining a width of the contact space, a back side source/drain contact electrically connected to the first source/drain region, filling the contact space, and having a sidewall facing each of the first and second fin portions and the device isolation film, and an etch stop layer contacting a top surface of each of the first and second fin portions between the first fin portion and the gate line.

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