公开(公告)号：US20250159871A1

公开(公告)日：2025-05-15

申请号：US18664850

申请日：2024-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Jun KIM ,  Ga Eun CHOI ,  Ji Hoon SUNG ,  Kyu Hyun CHA

IPC: H10B12/00

Abstract: A semiconductor memory device may include a substrate including a cell region, a peripheral region, and a boundary region therebetween, a plurality of gate electrodes extending in a first direction within the substrate of the cell region, a plurality of bit lines extending in a second direction crossing the first direction on the substrate of the cell region and the boundary region, a plurality of buried contacts connected to the substrate of the cell region and between the gate electrodes and between the bit lines on the substrate of the cell region, a dummy buried contact between the bit lines on the substrate of the boundary region, and a bit line contact connected to at least one of the bit lines on the substrate of the boundary region, wherein the dummy buried contact includes an insulating material.

公开(公告)号：US20240064968A1

公开(公告)日：2024-02-22

申请号：US18321511

申请日：2023-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Young CHOI ,  Hui-Jung KIM ,  Ji Hoon SUNG ,  Ga Eun CHOI ,  Sang Kyu SUN

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/485 ,  H10B12/02

Abstract: Provided is a semiconductor memory device comprising an active region extending in a cell isolation layer, wherein the active region includes a first region and a second region; a bit line intersects the active region; a bit line contact between a substrate and the bit line, wherein the bit line contact is electrically connected to the first region; a bit line spacer that is on side surfaces of the bit line and the bit line contact; a node pad on a lateral side of the bit line spacer, wherein the node pad is electrically connected to the second region; a storage contact that is on the node pad and on a side surface of the bit line spacer, wherein the storage contact includes a first part having a first width and a second part having a second width different from the first width.