公开(公告)号：US20250044222A1

公开(公告)日：2025-02-06

申请号：US18767486

申请日：2024-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Seungwoo LEE ,  Jinseob KIM ,  Jinyong KIM ,  Taejoong KIM ,  Jinwoo AHN ,  Jaehwang JUNG ,  Taeyong JO ,  Garam CHOI

IPC: G01N21/31 ,  G06T7/11

Abstract: An image measurement device includes an optical system that transmits light output to an image detection unit, the image detection unit configured to detect the light and generate an image, and an image processing unit that extracts spectral data from the image, wherein the image processing unit generates a profile according to an amount of light for each of a plurality of pixels based on the image, and performs Fourier transform on the profile.

公开(公告)号：US20220321112A1

公开(公告)日：2022-10-06

申请号：US17842881

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae CHOI ,  Garam CHOI

IPC: H03K5/156 ,  H03L7/081 ,  G11C8/18 ,  G11C7/22 ,  G11C8/10

Abstract: A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.

公开(公告)号：US20220006461A1

公开(公告)日：2022-01-06

申请号：US17149039

申请日：2021-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae CHOI ,  Garam CHOI

IPC: H03L7/081 ,  G11C11/4076

Abstract: A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to split a phase of a reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate configured to delay the second reference clock signal to output a delayed reference clock signal; and a delay line circuit including a plurality of delay cells that are cascade-connected, the delay line circuit configured to delay the first reference clock signal and the delayed reference clock signal based on a control code set, and to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to a delay of one logic gate included in the plurality of delay cells.

公开(公告)号：US20240230314A9

公开(公告)日：2024-07-11

申请号：US18317395

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Garam CHOI ,  Wookrae KIM ,  Jinseob KIM ,  Jinyong KIM ,  Sungho JANG ,  Younguk JIN ,  Daehoon HAN

IPC: G01B9/02 ,  G01B9/02097

CPC classification number: G01B9/02044 ,  G01B9/02097 ,  G01B2210/56 ,  G01B2290/70

Abstract: A semiconductor measurement apparatus may include an illumination unit configured to irradiate light to the sample, an image sensor configured to receive light reflected from the sample and output multiple interference images representing interference patterns of polarization components of light, an optical unit in a path through which the image sensor receives light and including an objective lens above the sample, and a control unit configured to obtain, by processing the multi-interference image, measurement parameters determined from the polarization components at each of a plurality of azimuth angles defined on a plane perpendicular to a path of light incident to the image sensor. The control unit may be configured to determine a selected critical dimension to be measured from a structure in the sample based on measurement parameters. The illumination unit and/or the optical unit may include a polarizer and a compensator having a ¼ wave plate.

公开(公告)号：US20240133673A1

公开(公告)日：2024-04-25

申请号：US18317395

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Garam CHOI ,  Wookrae KIM ,  Jinseob KIM ,  Jinyong KIM ,  Sungho JANG ,  Younguk JIN ,  Daehoon HAN

IPC: G01B9/02 ,  G01B9/02097

CPC classification number: G01B9/02044 ,  G01B9/02097 ,  G01B2210/56 ,  G01B2290/70

Abstract: A semiconductor measurement apparatus may include an illumination unit configured to irradiate light to the sample, an image sensor configured to receive light reflected from the sample and output multiple interference images representing interference patterns of polarization components of light, an optical unit in a path through which the image sensor receives light and including an objective lens above the sample, and a control unit configured to obtain, by processing the multi-interference image, measurement parameters determined from the polarization components at each of a plurality of azimuth angles defined on a plane perpendicular to a path of light incident to the image sensor. The control unit may be configured to determine a selected critical dimension to be measured from a structure in the sample based on measurement parameters. The illumination unit and/or the optical unit may include a polarizer and a compensator having a ¼ wave plate.

公开(公告)号：US20210335403A1

公开(公告)日：2021-10-28

申请号：US17109567

申请日：2020-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hundae CHOI ,  Garam CHOI

IPC: G11C7/22 ,  G11C8/10 ,  G11C7/10 ,  H03L7/081 ,  H03L7/085

Abstract: A delay locked loop circuit and a semiconductor memory device are provided. The delay locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal the feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, to detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and to change a code value in response to the first phase difference detection signal or the second phase difference detection signal.