公开(公告)号：US09842182B2

公开(公告)日：2017-12-12

申请号：US14845556

申请日：2015-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon Baek ,  Tae-Joong Song ,  Gi-Young Yang ,  Jeong-Ho Do

IPC: G06F17/50 ,  H01L29/66

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  H01L29/6681

Abstract: A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout.

公开(公告)号：US09324384B2

公开(公告)日：2016-04-26

申请号：US14504596

申请日：2014-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Joong Song ,  Sung-Hyun Park ,  Woo-Jin Rim ,  Gi-Young Yang

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C11/419

CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C11/419

Abstract: In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.

Abstract translation: 在感测放大器中，开关晶体管被配置为响应于感测使能信号而将接地电压施加到接地节点。 第一检测电路被配置为基于位线的模式信号和电压将第一检测信号输出到第一检测节点。 第二检测电路被配置为基于互补位线的电压将第二检测信号输出到第二检测节点。 锁存电路连接到电源电压，第一检测节点和第二检测节点，并且被配置为分别基于第一检测来通过锁存节点和互补锁存器节点输出第一放大信号和第二放大信号 信号和第二检测信号。

公开(公告)号：US09576953B2

公开(公告)日：2017-02-21

申请号：US14488628

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Hyun Baek ,  Jin-Hyun Noh ,  Tae-Joong Song ,  Gi-Young Yang ,  Sang-Kyu Oh

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L27/11 ,  G06F17/50

CPC classification number: H01L27/0886 ,  G06F17/5068 ,  H01L27/1104 ,  H01L29/785 ,  H01L29/7851

Abstract: A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.

Abstract translation: 用于设计半导体器件的布局设计系统包括处理器，存储中间设计的存储模块和由处理器用于校正中间设计的校正模块。 中间设计包括有源区域和有源区域的虚拟设计。 每个虚拟设计包括虚拟结构和设置在虚拟结构的相对侧的虚设间隔物。 校正模块被配置为改变至少一些虚拟设计的区域的宽度。 校正后的设计用于制造具有活性鳍片，设置在活性鳍片上的硬掩模层，与硬掩模层之间交叉的栅极结构以及设置在栅极结构的至少一侧上的间隔物的半导体器件。 硬掩模层和活动翅片具有由于虚拟设计而变化的宽度。