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    Semiconductor integrated circuits having contacts spaced apart from active regions
    2.
    发明授权
    Semiconductor integrated circuits having contacts spaced apart from active regions 有权

    公开(公告)号：US10083966B2

    公开(公告)日：2018-09-25

    申请号：US15656272

    申请日：2017-07-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae-Joong Song ,  Jung-Han Kim

    IPC: H01L27/092 ,  H01L27/02 ,  H03K3/356

    CPC classification number: H01L27/0928 ,  H01L27/0207 ,  H01L27/092 ,  H03K3/356156

    Abstract: First and second active regions are doped with different types of impurities, and extend in a first direction and spaced apart from each other in a second direction. First and third gate structures, which are on the first active region and a first portion of the isolation layer between the first and second active regions, extend in the second direction and are spaced apart from each other in the first direction. Second and fourth gate structures, which are on the second active region and the first portion, extend in the second direction, are spaced apart from each other in the first direction, and face and are spaced apart from the first and third gate structures, respectively, in the second direction. First to fourth contacts are on portions of the first to fourth gate structures, respectively. The first and fourth contacts are connected, and the second and third contacts are connected.

    Semiconductor memory devices with a power supply
    4.
    发明授权
    Semiconductor memory devices with a power supply 有权
    具有电源的半导体存储器件

    公开(公告)号：US09240223B2

    公开(公告)日：2016-01-19

    申请号：US14272881

    申请日：2014-05-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tae-Joong Song

    IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10

    CPC classification number: G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  Y10T307/406

    Abstract: A semiconductor device includes a virtual power supplier, a driving signal generator and a load driver. The virtual power supplier boosts a driving voltage to generate a virtual voltage. The driving signal generator generates a driving signal based on the virtual voltage, such that the driving signal has a voltage level that is reinforced as compared with a voltage level of the driving voltage. The load driver drives a load based on the driving voltage and the driving signal.

    Abstract translation: 半导体器件包括虚拟电源，驱动信号发生器和负载驱动器。 虚拟电源提供驱动电压以产生虚拟电压。 驱动信号发生器基于虚拟电压生成驱动信号，使得驱动信号具有与驱动电压的电压电平相比被加强的电压电平。 负载驱动器根据驱动电压和驱动信号驱动负载。

    Resistive memory device having reduced chip size and operation method thereof
    7.
    发明授权
    Resistive memory device having reduced chip size and operation method thereof 有权

    公开(公告)号：US10373664B2

    公开(公告)日：2019-08-06

    申请号：US15919876

    申请日：2018-03-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Suk-Soo Pyo ,  Hyun-Taek Jung ,  Tae-Joong Song

    IPC: G11C11/00 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00

    Abstract: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.

    INTEGRATED CIRCUIT INCLUDING A MODIFIED CELL AND A METHOD OF DESIGNING THE SAME
    8.
    发明申请
    INTEGRATED CIRCUIT INCLUDING A MODIFIED CELL AND A METHOD OF DESIGNING THE SAME 审中-公开

    公开(公告)号：US20180096092A1

    公开(公告)日：2018-04-05

    申请号：US15585548

    申请日：2017-05-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JIN-TAE KIM ,  Jung-Ho Do ,  Tae-Joong Song ,  Doo-Hee Cho ,  Seung-Young Lee

    IPC: G06F17/50

    Abstract: A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.

    Layout design system, semiconductor device fabricated by using the system and method for fabricating the semiconductor device
    9.
    发明授权
    Layout design system, semiconductor device fabricated by using the system and method for fabricating the semiconductor device 有权
    布局设计系统，通过使用该系统制造的半导体器件和用于制造半导体器件的方法

    公开(公告)号：US09576953B2

    公开(公告)日：2017-02-21

    申请号：US14488628

    申请日：2014-09-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kang-Hyun Baek ,  Jin-Hyun Noh ,  Tae-Joong Song ,  Gi-Young Yang ,  Sang-Kyu Oh

    IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L27/11 ,  G06F17/50

    CPC classification number: H01L27/0886 ,  G06F17/5068 ,  H01L27/1104 ,  H01L29/785 ,  H01L29/7851

    Abstract: A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.

    Abstract translation: 用于设计半导体器件的布局设计系统包括处理器，存储中间设计的存储模块和由处理器用于校正中间设计的校正模块。 中间设计包括有源区域和有源区域的虚拟设计。 每个虚拟设计包括虚拟结构和设置在虚拟结构的相对侧的虚设间隔物。 校正模块被配置为改变至少一些虚拟设计的区域的宽度。 校正后的设计用于制造具有活性鳍片，设置在活性鳍片上的硬掩模层，与硬掩模层之间交叉的栅极结构以及设置在栅极结构的至少一侧上的间隔物的半导体器件。 硬掩模层和活动翅片具有由于虚拟设计而变化的宽度。

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