公开(公告)号：US20220139766A1

公开(公告)日：2022-05-05

申请号：US17578785

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso SHIN ,  Chungki MIN ,  Gihwan KIM ,  Sanghyeok KIM ,  Hyo-Jung KIM ,  Geunwon LIM

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/11573 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/311

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

公开(公告)号：US20210375905A1

公开(公告)日：2021-12-02

申请号：US17140277

申请日：2021-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changsun HWANG ,  Youngjin KWON ,  Gihwan KIM ,  Hansol SEOK ,  Dongseog EUN ,  Jongheun LIM

IPC: H01L27/11573 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.

公开(公告)号：US20200075398A1

公开(公告)日：2020-03-05

申请号：US16377516

申请日：2019-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso SHIN ,  Chungki MIN ,  Gihwan KIM ,  Sanghyeok KIM ,  Hyo-Jung KIM ,  Geunwon LIM

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/324 ,  H01L27/11582 ,  H01L27/11573

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.