公开(公告)号：US20240215242A1

公开(公告)日：2024-06-27

申请号：US18475784

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gil Sung LEE ,  Suk Kang SUNG

IPC: H10B43/27 ,  G11C16/04 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06503

Abstract: A semiconductor memory device may include a cell substrate, a mold structure including gate electrodes stacked on the cell substrate, a channel structures penetrating the mold structure; and a first cutting structure cutting some of the gate electrodes. The first cutting structure may include a first portion having a line shape extending in a first direction and a second portion having a line shape extending in a second direction. The first portion and the second portion may be alternately connected to form a zigzag shape. The first cutting structure may include a first side wall and a second side wall opposing the first side wall. A first point of the first side wall connected from the second portion to the first portion and a second point of the second side wall connected from the first portion to the second portion may be in corresponding channel structures among the channel structures.

公开(公告)号：US20230114139A1

公开(公告)日：2023-04-13

申请号：US17900172

申请日：2022-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Joon Sung KIM ,  Suk Kang SUNG ,  Gil Sung LEE ,  Jong-Min LEE

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.