公开(公告)号：US11601131B2

公开(公告)日：2023-03-07

申请号：US17734693

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangdon Jung ,  Gyusik Kim ,  Seungjin Kim ,  Seunghyun Oh ,  Jihwan Kim

IPC: H03L7/10 ,  H03L7/099 ,  H03L7/089

Abstract: A phase locked loop includes a phase detector outputting a first signal corresponding to a phase difference of a reference frequency signal and a division frequency signal, a charge pump amplifying a first signal to output a second signal, a loop filter filtering the second signal to output a third signal, a voltage-to-current converter receiving the third signal and outputting a fourth signal, a digital-to-analog converter outputting a fifth signal based on the fourth signal and a digital compensation signal, an oscillator outputting an output frequency signal having a frequency corresponding to the fifth signal, a divider dividing the frequency of the output frequency signal to output the division frequency signal and a compensation frequency signal, and an automatic frequency calibrator compensating for the voltage-to-current converter based on a difference between a frequency of the compensation frequency signal and a frequency of a reference frequency signal.

公开(公告)号：US11962311B2

公开(公告)日：2024-04-16

申请号：US17865811

申请日：2022-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyusik Kim ,  Seungjin Kim ,  Seunghyun Oh

IPC: H03L7/091 ,  H03L7/099

CPC classification number: H03L7/091 ,  H03L7/099

Abstract: A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.