公开(公告)号：US11601131B2

公开(公告)日：2023-03-07

申请号：US17734693

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangdon Jung ,  Gyusik Kim ,  Seungjin Kim ,  Seunghyun Oh ,  Jihwan Kim

IPC: H03L7/10 ,  H03L7/099 ,  H03L7/089

Abstract: A phase locked loop includes a phase detector outputting a first signal corresponding to a phase difference of a reference frequency signal and a division frequency signal, a charge pump amplifying a first signal to output a second signal, a loop filter filtering the second signal to output a third signal, a voltage-to-current converter receiving the third signal and outputting a fourth signal, a digital-to-analog converter outputting a fifth signal based on the fourth signal and a digital compensation signal, an oscillator outputting an output frequency signal having a frequency corresponding to the fifth signal, a divider dividing the frequency of the output frequency signal to output the division frequency signal and a compensation frequency signal, and an automatic frequency calibrator compensating for the voltage-to-current converter based on a difference between a frequency of the compensation frequency signal and a frequency of a reference frequency signal.

公开(公告)号：US10921847B2

公开(公告)日：2021-02-16

申请号：US16724754

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangdon Jung ,  Jaehong Jung ,  Seunghyun Oh ,  Kyungmin Lee

IPC: G06F1/08 ,  H03L7/097 ,  H03L7/08

Abstract: The clock generator is provided and includes a phase detector, a voltage generator, a voltage-to-current converter, and an oscillation circuit. The voltage generator generates a control voltage. The voltage-to-current converter converts the control voltage into an internal current having a level based on a resistance value of a resistor circuit, the resistance value set based on first control information. The oscillation circuit generates a output clock having a frequency based on the level of the internal current and a capacitance value of a capacitor circuit, the capacitance value set based on second control information. The clock generator maintains a frequency value and varies jitter characteristics of the output clock in response to the first control information and the second control information.

公开(公告)号：US10483984B2

公开(公告)日：2019-11-19

申请号：US15803026

申请日：2017-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangdon Jung ,  Dokyung Lim ,  Wooseok Kim

IPC: H03L1/02 ,  H03B5/04 ,  H03B5/32 ,  H03B5/36 ,  H03B5/08

Abstract: A temperature compensated oscillation controller includes a temperature compensation circuit configured to provide a reference voltage through a first terminal and to receive an input voltage including temperature information through a second terminal, and an oscillation circuit configured to be connected to an external crystal resonator through third and fourth terminals and to output a clock signal in response to an oscillation signal from the external crystal resonator. The temperature compensation circuit is configured to perform a voltage controlled oscillator-based sensing operation to convert the input voltage into a temperature code and to adjust a frequency of the clock signal using the temperature code.

公开(公告)号：US11057040B2

公开(公告)日：2021-07-06

申请号：US17006152

申请日：2020-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehong Jung ,  Sangdon Jung ,  Kyungmin Lee ,  Byungki Han

IPC: H03L7/081 ,  H03L7/091 ,  H03L7/197 ,  H03L7/099

Abstract: A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.