公开(公告)号：US11467195B2

公开(公告)日：2022-10-11

申请号：US16781333

申请日：2020-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolhwan Lim ,  Youngbin Kwon ,  Yongjin Lee ,  Haejung Choi ,  Kwangho Kim

IPC: G01R19/165 ,  G01R19/00 ,  H03K17/22 ,  H03K17/284

Abstract: A voltage monitoring circuit includes an initializing circuit that outputs an initialization signal generated by delaying a power supply voltage as much as a first delay time, a switching circuit that outputs a switching signal in response to a reset signal, a voltage detecting circuit that outputs a detection signal based on the power supply voltage and stops an operation in response to the switching signal, and an output circuit that outputs the reset signal based on the initialization signal and the detection signal.

公开(公告)号：US11650232B2

公开(公告)日：2023-05-16

申请号：US17872363

申请日：2022-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolhwan Lim ,  Junhee Shin ,  Haejung Choi ,  Kwangho Kim ,  Hyunmyoung Kim

IPC: G01R19/165 ,  H03K17/687 ,  H03K3/037 ,  G06F1/24 ,  G06F1/28

CPC classification number: G01R19/165 ,  G06F1/24 ,  G06F1/28 ,  H03K3/037 ,  H03K17/6872

Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.

公开(公告)号：US12230588B2

公开(公告)日：2025-02-18

申请号：US17860699

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheolhwan Lim ,  Kwangho Kim ,  Sangjin Lim ,  Haejung Choi ,  Donghun Heo

IPC: G11C29/12 ,  G01J1/42 ,  H01L23/00 ,  H03K19/003

Abstract: A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.