公开(公告)号：US20240213199A1

公开(公告)日：2024-06-27

申请号：US18227646

申请日：2023-07-28

申请人： Samsung Electronics Co., Ltd.

发明人： Sungwoo PARK ,  Yongjae KIM ,  Heonwoo KIM ,  Seung-Kwan RYU

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L24/13 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/13017 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/37001

摘要： The present disclosure provides semiconductor packages and methods of fabricating the same. In some embodiments, a semiconductor package includes a substrate including first and second regions, a first pad on the first region, a second pad on the second region, a first dielectric layer on the first region and including a first opening exposing the first pad, a second dielectric layer on the second region and including a second opening exposing the second pad, a first bump structure on the first pad and in the first opening, and a second bump structure on the second pad and in the second opening. A thickness of the first dielectric layer is greater than a thickness of the second dielectric layer. A distance between the substrate and an uppermost end of the first bump structure is longer than a distance between the substrate and an uppermost end of the second bump structure.

公开(公告)号：US20220199577A1

公开(公告)日：2022-06-23

申请号：US17478247

申请日：2021-09-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungwoo PARK ,  Ungcheon KIM ,  Heonwoo KIM ,  Yunseok CHOI

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

摘要： A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction.