公开(公告)号：US20170345946A1

公开(公告)日：2017-11-30

申请号：US15666844

申请日：2017-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho LEE ,  Ho Jun KIM ,  Sung Dae SUK ,  Geum Jong BAE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545

Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.

公开(公告)号：US20240136290A1

公开(公告)日：2024-04-25

申请号：US18323006

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jee Woong KIM ,  Jin Kyu KIM ,  Ho Jun KIM ,  Jae Hyun AHN ,  So Ra YOU

IPC: H01L23/528 ,  H01L23/48 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L29/41725 ,  H01L29/78

Abstract: A semiconductor device having simplicity in design and improved performance and methods for fabricating the same are provided. The semiconductor device includes a substrate including a frontside and a backside opposite the frontside, an electronic device on the frontside of the substrate, an interlayer insulating layer covering the electronic device, a frontside wiring structure on the interlayer insulating layer, a backside wiring structure on the backside of the substrate, and at least one unit chain connecting the electronic device with the backside wiring structure, the unit chain including a through plug passing through the substrate, a connection contact on the interlayer insulating layer, a first chain plug passing through the interlayer insulating layer to connect the through plug with the connection contact, and a second chain plug passing through the interlayer insulating layer to be connected to the through plug.

公开(公告)号：US20240234319A9

公开(公告)日：2024-07-11

申请号：US18323006

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jee Woong KIM ,  Jin Kyu KIM ,  Ho Jun KIM ,  Jae Hyun AHN ,  So Ra YOU

IPC: H01L23/528 ,  H01L23/48 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L29/41725 ,  H01L29/78

Abstract: A semiconductor device having simplicity in design and improved performance and methods for fabricating the same are provided. The semiconductor device includes a substrate including a frontside and a backside opposite the frontside, an electronic device on the frontside of the substrate, an interlayer insulating layer covering the electronic device, a frontside wiring structure on the interlayer insulating layer, a backside wiring structure on the backside of the substrate, and at least one unit chain connecting the electronic device with the backside wiring structure, the unit chain including a through plug passing through the substrate, a connection contact on the interlayer insulating layer, a first chain plug passing through the interlayer insulating layer to connect the through plug with the connection contact, and a second chain plug passing through the interlayer insulating layer to be connected to the through plug.

公开(公告)号：US20170250291A1

公开(公告)日：2017-08-31

申请号：US15222276

申请日：2016-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho LEE ,  Ho Jun KIM ,  Sung Dae SUK ,  Geum Jong BAE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545

Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.