公开(公告)号：US20170221755A1

公开(公告)日：2017-08-03

申请号：US15398090

申请日：2017-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang SIM ,  Hojun SEONG ,  Bongtae PARK ,  Woo-Jung KIM

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/11529 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11573

Abstract: A semiconductor device may include a first conductive pattern having a line portion and a pad portion connected to the line portion on a substrate, a gate insulating pattern and a second conductive pattern sequentially stacked on the substrate, and a capping layer disposed on the first and second conductive patterns. A first trench is defined in an upper portion of the substrate adjacent to one side of the second conductive pattern, and the capping layer at least partially fills the first trench.

公开(公告)号：US20220367511A1

公开(公告)日：2022-11-17

申请号：US17729549

申请日：2022-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younjeong HWANG ,  Minbum KIM ,  Hojun SEONG ,  Sung-Hun LEE ,  Juneon JIN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528

Abstract: A three-dimensional semiconductor memory device may include a source structure on a substrate, a stack structure including electrode layers and inter-electrode insulating layers, which are on the source structure and are alternately stacked, a vertical structure penetrating the stack structure and the source structure and being adjacent to the substrate, and a separation insulation pattern penetrating the stack structure and the source structure and being spaced apart from the vertical structure. The uppermost one of the inter-electrode insulating layers may include a first impurity injection region located at a first height from a top surface of the substrate. The stack structure may define a groove, in which the separation insulation pattern is located. An inner sidewall of the groove may define a recess region, which is located at the first height from the top surface of the substrate and is recessed toward the vertical structure.

公开(公告)号：US20150325478A1

公开(公告)日：2015-11-12

申请号：US14665141

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun SEONG ,  Jae-Hwang SIM ,  Jeehoon HAN

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines.

Abstract translation: 制造半导体器件的方法包括在衬底的第一表面上堆叠蚀刻目标层，第一掩模层和第二掩模层。 多个第一间隔线彼此平行地形成，并且形成第二掩模层上的第一间隔垫线。 形成与第二掩模层上的至少第一间隔垫线接触的第三掩模焊盘。 蚀刻第二掩模层和第一掩模层以形成一个或多个第一掩模线，第一掩模预焊垫和第二掩模图案。 分别形成覆盖第一掩模预备焊盘和第一掩模线的侧壁的第二间隔线。 形成第一掩模垫。 蚀刻目标层被蚀刻以形成连接到导线的导电线和导电焊盘。