RANDOM NUMBER GENERATORS AND METHODS OF GENERATING RANDOM NUMBERS USING ADJUSTABLE META-STABLE VOLTAGE

    公开(公告)号:US20180143806A1

    公开(公告)日:2018-05-24

    申请号:US15634276

    申请日:2017-06-27

    IPC分类号: G06F7/58

    CPC分类号: G06F7/582 G06F7/588

    摘要: A random number generator may include a first meta-stable inverter having an input terminal and an output terminal connected to each other and configured to generate a meta-stable voltage, an amplifier configured to amplify the meta-stable voltage, control circuitry configured to adjust a threshold voltage of the meta-stable voltage, and a sampler configured to generate a random number based on sampling the meta-stable voltage. The random number generator may be configured to be operated according to different modes of operation of a plurality of modes of operation. The amplifier may be a second meta-stable inverter configured to amplify the meta-stable voltage or include an input terminal and an output terminal that are connected to each other based on the random number generator being operated according to a first mode of operation or a second mode of operation, respectively, of the plurality of modes of operation.

    MODULAR MULTIPLIER AND MODULAR MULTIPLICATION METHOD THEREOF
    3.
    发明申请
    MODULAR MULTIPLIER AND MODULAR MULTIPLICATION METHOD THEREOF 有权
    模块化乘法器和模块化乘法方法

    公开(公告)号:US20130311533A1

    公开(公告)日:2013-11-21

    申请号:US13792642

    申请日:2013-03-11

    IPC分类号: G06F7/72

    CPC分类号: G06F7/722 G06F7/728

    摘要: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.

    摘要翻译: 提供了一种模数乘法器和一种模乘法。 模数乘法器包括:第一寄存器,其存储在先前周期计算的先前累积值; 存储在前一周期计算的先前商的第二寄存器; 商产生器,其使用从所述第一寄存器输出的存储的先前累积值生成商; 以及累加器,其接收操作数,乘数的位值,存储的先前累积值和存储的先前商,以计算当前周期中的累加值,其中计算的累积值被更新为第一寄存器,并且 生成商被更新到第二个寄存器。

    SEMICONDUCTOR DEVICES AND METHODS OF PROTECTING DATA OF CHANNELS IN THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF PROTECTING DATA OF CHANNELS IN THE SAME 审中-公开
    半导体器件及其保护通道数据的方法

    公开(公告)号:US20150372816A1

    公开(公告)日:2015-12-24

    申请号:US14713120

    申请日:2015-05-15

    IPC分类号: H04L9/14 G06F13/42 G06F21/60

    摘要: A semiconductor device may include: a bus; first and second function modules configured to communicate via the bus; a first encryption module configured to encrypt first data output from the first function module using a first encryption key to generate first encrypted data; and/or a second encryption module configured to decrypt the first encrypted data using the first encryption key, to output the decrypted first data to the second function module, and to encrypt second data output from the second function module using a second encryption key to generate second encrypted data. A semiconductor device may include: a bus; first and second modules configured to communicate via the bus; and/or an encryption module configured to use different encryption policies for first data, which is output from the first module and stored in a memory, and second data, which is output from the second module and stored in the memory.

    摘要翻译: 半导体器件可以包括:总线; 配置为经由总线通信的第一和第二功能模块; 第一加密模块,被配置为使用第一加密密钥来加密从所述第一功能模块输出的第一数据,以生成第一加密数据; 和/或第二加密模块,被配置为使用第一加密密钥对第一加密数据进行解密,以将解密的第一数据输出到第二功能模块,并且使用第二加密密钥来加密从第二功能模块输出的第二数据,以产生 第二个加密数据。 半导体器件可以包括:总线; 第一和第二模块经配置以经由总线进行通信; 和/或被配置为对从第一模块输出并存储在存储器中的第一数据使用不同的加密策略的加密模块以及从第二模块输出并存储在存储器中的第二数据。

    ENCODER AND METHOD FOR ENCODING THEREOF
    5.
    发明申请
    ENCODER AND METHOD FOR ENCODING THEREOF 有权
    编码器及其编码方法

    公开(公告)号:US20150254476A1

    公开(公告)日:2015-09-10

    申请号:US14577608

    申请日:2014-12-19

    IPC分类号: G06F21/72

    摘要: A method of encoding and an encoder are provided. The method includes generating first one-hot bits for most significant bits (MSBs) and second one-hot bits for least significant bits (LSBs) using input one-hot bits; encoding the first one-hot bits to the MSBs and complementary MSBs through a first logical operation using a cross-connection; and encoding the second one-hot bits to the LSBs and complementary LSBs through a second logical operation using a cross-connection. The encoder includes a first bit generator, a first encoder, a second bit generator and a second encoder.

    摘要翻译: 提供了一种编码方法和编码器。 该方法包括使用输入单热位产生用于最高有效位(MSB)的第一单热位和用于最低有效位(LSB)的第一单热位; 通过使用交叉连接的第一逻辑运算将第一单热比特编码到MSB和互补MSB; 以及通过使用交叉连接的第二逻辑运算将第二单热比特编码到LSB和互补LSB。 编码器包括第一位发生器,第一编码器,第二位发生器和第二编码器。