公开(公告)号：US20140008598A1

公开(公告)日：2014-01-09

申请号：US14017856

申请日：2013-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

IPC: H01L45/00

CPC classification number: H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

Abstract translation: 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

公开(公告)号：US09053963B2

公开(公告)日：2015-06-09

申请号：US13938314

申请日：2013-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chung-ki Lee ,  Hong-sun Hwang ,  Hyung-shin Kwon ,  Jong-hyoung Lim

IPC: G11C7/00 ,  H01L27/088 ,  G11C11/40 ,  G11C11/404 ,  G11C11/408 ,  H01L27/108 ,  G11C11/4094

CPC classification number: H01L27/088 ,  G11C11/40 ,  G11C11/404 ,  G11C11/4085 ,  G11C11/4094 ,  G11C2207/005 ,  H01L27/10897

Abstract: A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage.

Abstract translation: 一种包括半导体衬底的多阱偏压存储器件; 第一导电类型的第一阱形成在半导体衬底中并具有形成在其中的存储单元; 以及形成在半导体衬底中的第一导电类型的第二阱，并且其中形成有用于感测和放大来自存储器单元的数据的读出放大器。 第一和第二阱具有不同的掺杂浓度并分别偏置到第一和第二电压。 第一电压低于第二电压。

公开(公告)号：US08730710B2

公开(公告)日：2014-05-20

申请号：US14017856

申请日：2013-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

IPC: G11C11/00

CPC classification number: H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

Abstract translation: 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。