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公开(公告)号:US11450545B2
公开(公告)日:2022-09-20
申请号:US16683707
申请日:2019-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jongwoo Sun , Incheol Song , Hongmin Yoon , Jihyun Lim , Masayuki Tomoyasu , Jewoo Han
IPC: H01L21/683 , H01J37/32
Abstract: According to some embodiments, a semiconductor substrate processing apparatus includes a housing, a plasma source unit, an electrostatic chuck, and a ring unit. The housing encloses a process chamber. The plasma source unit is connected to the housing, and includes a shower head and a fixing ring positioned to support the shower head. The shower head includes an upper electrode mounted on the fixing ring, and includes injection holes passing through part of the upper electrode and configured to inject gas into the chamber. The electrostatic chuck is connected to the housing and includes a lower electrode, and is for mounting a semiconductor substrate thereon. The ring unit is mounted on an edge portion of the electrostatic chuck, and includes a focus ring and a cover ring surrounding the focus ring. One of the lower electrode and the upper electrode is connected to a high frequency power supply, and the other of the lower electrode and the upper electrode is connected to ground. The focus ring has an inner side surface, and an opposite outer side surface that contacts the cover ring, and a width between the inner side surface and the outer side surface of the focus ring is a first width. The cover ring has an inner side surface that contacts the outer side surface of the focus ring, and an outer side surface, and a width between the inner side surface and the outer side surface of the cover ring is a second width. The first width is between 2 and 10 time the second width.
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2.
公开(公告)号:US11817298B2
公开(公告)日:2023-11-14
申请号:US17108037
申请日:2020-12-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Incheol Song , Masayuki Tomoyasu , Hongmin Yoon , Jihyun Lim
IPC: H01J37/32
CPC classification number: H01J37/32642 , H01J37/32174 , H01J37/32715 , H01J2237/3341
Abstract: A focus ring includes a first conductive layer having a first thickness and a first specific resistance, a second conductive layer stacked on the first conductive layer, the second conductive layer having a second thickness greater than the first thickness and a second specific resistance greater than the first specific resistance, and a dielectric layer on one of a lower surface of the first conductive layer and an upper surface of the second conductive layer.
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