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公开(公告)号:US20240347508A1
公开(公告)日:2024-10-17
申请号:US18584007
申请日:2024-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jihyun Lim
IPC: H01L25/065 , H01L23/00 , H01L23/04 , H01L23/31 , H01L23/538 , H01L25/10
CPC classification number: H01L25/0655 , H01L23/041 , H01L23/3107 , H01L23/5383 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/06568
Abstract: A semiconductor package includes a lower redistribution wiring layer having lower redistribution wirings; an encapsulation structure on the lower redistribution wiring layer; a plurality of conductive bumps between the lower redistribution wiring layer and the encapsulation structure; and an adhesive layer attaching the lower redistribution wiring layer and the encapsulation structure. The encapsulation structure includes a core substrate having a cavity formed therein, at least one semiconductor chip in the cavity such that a front surface on which chip pads are formed faces the lower redistribution wiring layer, and an upper redistribution wiring layer covering an upper surface of the core substrate and having upper redistribution wiring layers that are electrically connected to conductive structures of the core substrate.
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公开(公告)号:US11023137B2
公开(公告)日:2021-06-01
申请号:US16415068
申请日:2019-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyung-San Kim , Kyung Ho Kim , Seokhwan Kim , Seunguk Shin , Jihyun Lim
Abstract: A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
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3.
公开(公告)号:US11817298B2
公开(公告)日:2023-11-14
申请号:US17108037
申请日:2020-12-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Incheol Song , Masayuki Tomoyasu , Hongmin Yoon , Jihyun Lim
IPC: H01J37/32
CPC classification number: H01J37/32642 , H01J37/32174 , H01J37/32715 , H01J2237/3341
Abstract: A focus ring includes a first conductive layer having a first thickness and a first specific resistance, a second conductive layer stacked on the first conductive layer, the second conductive layer having a second thickness greater than the first thickness and a second specific resistance greater than the first specific resistance, and a dielectric layer on one of a lower surface of the first conductive layer and an upper surface of the second conductive layer.
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公开(公告)号:US20190272107A1
公开(公告)日:2019-09-05
申请号:US16415068
申请日:2019-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyung-San Kim , Kyung Ho Kim , Seokhwan Kim , Seunguk Shin , Jihyun Lim
Abstract: A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
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公开(公告)号:US20250079421A1
公开(公告)日:2025-03-06
申请号:US18757626
申请日:2024-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jihyun Lim , Yoonyoung Jeon
IPC: H01L25/16 , H01L23/00 , H01L23/498
Abstract: Provided is a semiconductor package including a first wiring structure, a second wiring structure disposed on the first wiring structure, an expanded layer electrically connecting the first wiring structure and the second wiring structure to each other, and including an expanded base layer and a plurality of via structures, a semiconductor chip disposed in the expanded layer and between the first wiring structure and the second wiring structure, and a buried capacitor structure including a plurality first through-holes spaced apart from each other that penetrate the expanded base layer adjacent to the semiconductor chip, and extend in a first horizontal direction along a side surface of the semiconductor chip, and a plurality of electrode layers disposed on sidewalls of the plurality of first through-holes.
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公开(公告)号:US11543968B2
公开(公告)日:2023-01-03
申请号:US17307098
申请日:2021-05-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyung-San Kim , Kyung Ho Kim , Seokhwan Kim , Seunguk Shin , Jihyun Lim
Abstract: A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
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公开(公告)号:US11450545B2
公开(公告)日:2022-09-20
申请号:US16683707
申请日:2019-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jongwoo Sun , Incheol Song , Hongmin Yoon , Jihyun Lim , Masayuki Tomoyasu , Jewoo Han
IPC: H01L21/683 , H01J37/32
Abstract: According to some embodiments, a semiconductor substrate processing apparatus includes a housing, a plasma source unit, an electrostatic chuck, and a ring unit. The housing encloses a process chamber. The plasma source unit is connected to the housing, and includes a shower head and a fixing ring positioned to support the shower head. The shower head includes an upper electrode mounted on the fixing ring, and includes injection holes passing through part of the upper electrode and configured to inject gas into the chamber. The electrostatic chuck is connected to the housing and includes a lower electrode, and is for mounting a semiconductor substrate thereon. The ring unit is mounted on an edge portion of the electrostatic chuck, and includes a focus ring and a cover ring surrounding the focus ring. One of the lower electrode and the upper electrode is connected to a high frequency power supply, and the other of the lower electrode and the upper electrode is connected to ground. The focus ring has an inner side surface, and an opposite outer side surface that contacts the cover ring, and a width between the inner side surface and the outer side surface of the focus ring is a first width. The cover ring has an inner side surface that contacts the outer side surface of the focus ring, and an outer side surface, and a width between the inner side surface and the outer side surface of the cover ring is a second width. The first width is between 2 and 10 time the second width.
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公开(公告)号:US10318174B2
公开(公告)日:2019-06-11
申请号:US15598850
申请日:2017-05-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyung-San Kim , Kyung Ho Kim , Seokhwan Kim , Seunguk Shin , Jihyun Lim
Abstract: A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
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