公开(公告)号：US10553273B2

公开(公告)日：2020-02-04

申请号：US16032822

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Woo Ryu ,  Kyungryun Kim ,  Soo Hwan Kim ,  Huikap Yang

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4097 ,  G11C11/4093

Abstract: A semiconductor memory device includes a cell array that includes a first row block and a second row block, a bit line sense amplifier block that senses data stored in the first row block or the second row block, a local sense amplifier that latches the sensed data transferred from the bit line sense amplifier block, and a switch that connects the local sense amplifier with a selected one of a first global data line and a second global data line in response to a select signal. The second row block may be placed at an edge of the cell array, and the switch connects the local sense amplifier with the first global data line when the first row block is activated and connects the local sense amplifier with the second global data line when the second row block is activated.

公开(公告)号：US10910028B2

公开(公告)日：2021-02-02

申请号：US16872429

申请日：2020-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Jin Kim ,  Huikap Yang

IPC: G11C7/00 ,  G11C8/10 ,  G11C17/16 ,  G06F11/20 ,  G11C17/18

Abstract: A memory device includes a bank that includes first memory cells connected to a first column selection line and second memory cells connected to a second column selection line, a first column decoder that selects the first memory cells by transmitting a first column selection signal in a first direction through the first column selection line, and a second column decoder that selects the second memory cells by transmitting a second column selection signal in a second direction opposite to the first direction through the second column selection line. The first column decoder includes a first register that stores a first fail column address of the first memory cells, and a second register that stores a second fail column address of the second memory cells.

公开(公告)号：US10685690B2

公开(公告)日：2020-06-16

申请号：US16222114

申请日：2018-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Jin Kim ,  Huikap Yang

IPC: G11C7/00 ,  G11C8/10 ,  G11C17/16 ,  G06F11/20 ,  G11C17/18

Abstract: A memory device includes a bank that includes first memory cells connected to a first column selection line and second memory cells connected to a second column selection line, a first column decoder that selects the first memory cells by transmitting a first column selection signal in a first direction through the first column selection line, and a second column decoder that selects the second memory cells by transmitting a second column selection signal in a second direction opposite to the first direction through the second column selection line. The first column decoder includes a first register that stores a first fail column address of the first memory cells, and a second register that stores a second fail column address of the second memory cells.

公开(公告)号：US20190378551A1

公开(公告)日：2019-12-12

申请号：US16222114

申请日：2018-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Jin Kim ,  Huikap Yang

IPC: G11C8/10 ,  G11C17/16 ,  G11C17/18 ,  G06F11/20

Abstract: A memory device includes a bank that includes first memory cells connected to a first column selection line and second memory cells connected to a second column selection line, a first column decoder that selects the first memory cells by transmitting a first column selection signal in a first direction through the first column selection line, and a second column decoder that selects the second memory cells by transmitting a second column selection signal in a second direction opposite to the first direction through the second column selection line. The first column decoder includes a first register that stores a first fail column address of the first memory cells, and a second register that stores a second fail column address of the second memory cells.