公开(公告)号：US20160195804A1

公开(公告)日：2016-07-07

申请号：US14972258

申请日：2015-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munja KIM ,  Ji-Beom YOO ,  Sooyoung KIM ,  Taesung KIM ,  Dong-Wook SHIN ,  Hwanchul JEON ,  Seul-Gi KIM

IPC: G03F1/64 ,  C23C16/44

CPC classification number: G03F1/62 ,  C23C16/26

Abstract: The method includes forming a graphite layer on a substrate, forming a supporting layer on the graphite layer to form a stack of the graphite layer and the supporting layer, removing the substrate to separate the stack from the substrate, transferring the stack of the graphite layer and the supporting layer onto a frame, and removing the supporting layer from the frame.

Abstract translation: 该方法包括在基底上形成石墨层，在石墨层上形成支撑层，形成石墨层和支撑层的叠层，去除衬底以将堆叠与衬底分离，转移石墨层的堆叠 和支撑层到框架上，并且从框架移除支撑层。

公开(公告)号：US20230301068A1

公开(公告)日：2023-09-21

申请号：US18118766

申请日：2023-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanchul JEON ,  Yeonsu KIM ,  Youngsik LEE ,  Hyuk KIM ,  Sangwuk PARK

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/315 ,  H01L23/5283 ,  H10B12/05

Abstract: A semiconductor memory device includes a substrate, contact electrodes extending in a first direction, each of the contact electrodes including a connection portion having a first thickness and a landing portion having a second thickness, an uppermost contact electrode above the contact electrodes, the contact electrodes being longer in the first direction than the uppermost contact electrode and defining a step structure, transistor bodies extending in a second direction and having a first source/drain, a monocrystalline channel layer, and a second source/drain sequentially arranged in the second direction, the monocrystalline channel layer being connected to a corresponding contact electrode, a lower electrode layer connected to the second source/drain of each of the transistor bodies, a capacitor dielectric layer covering the lower electrode layer and having a uniform thickness, and an upper electrode layer separated from the lower electrode layer by the capacitor dielectric layer.

公开(公告)号：US20180203346A1

公开(公告)日：2018-07-19

申请号：US15919653

申请日：2018-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanchul JEON ,  Munja KIM ,  Sungwon KWON ,  Byunggook KIM ,  Roman CHALYKH ,  Yongseok JUNG ,  Jaehyuck CHOI

IPC: G03F1/64 ,  G03F1/62

CPC classification number: G03F1/64 ,  G03F1/62

Abstract: A pellicle for lithography processes, including extreme ultraviolet (EUV) lithography may mitigate thermal accumulation in a membrane of the pellicle. The pellicle includes a membrane and at least one thermal buffer layer on at least one surface of the membrane. An emissivity of the thermal buffer layer may be greater than an emissivity of the membrane. A carbon content of the thermal buffer layer may be greater than a carbon content of the membrane. Multiple thermal buffer layers may be on separate surfaces of the membrane, and the thermal buffer layers may have different properties. A capping layer may be on at least one thermal buffer layer, and the capping layer may include a hydrogen resistant material. A thermal buffer layer may extend over some or all of a surface of the membrane. A thermal buffer layer may be between at least two membranes.