公开(公告)号：US20240311302A1

公开(公告)日：2024-09-19

申请号：US18589852

申请日：2024-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Jung ,  Daehoon Kim ,  Hwanjun Lee ,  Jonggeon Lee ,  Jinin So

IPC: G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0811 ,  G06F12/084

Abstract: A processor includes a processing core configured to process each of a plurality of requests by accessing a corresponding one of a first memory and a second memory, a latency monitor configured to generate first latency information and second latency information, the first latency information comprising a first access latency to the first memory, and the second latency information comprising a second access latency to the second memory, a plurality of cache ways divided into a first partition and a second partition, and a decision engine configured to allocate each of the plurality of cache ways to one of the first partition and the second partition, based on the first latency information and the second latency information.

公开(公告)号：US20250077433A1

公开(公告)日：2025-03-06

申请号：US18604783

申请日：2024-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehoon Kim ,  Hyungwon Park ,  Jin Jung ,  Minho Kim ,  Jin In So ,  Jong-Geon Lee ,  Hwanjun Lee ,  Minwoo Jang ,  Yeaji Jung

IPC: G06F12/0862

Abstract: Memory systems and methods for operating the same. A memory system comprises a first memory, a second memory having an operating speed different from that of the first memory, a storage unit configured to store an instruction, a prefetcher configured to update prefetcher data in response to occurrence of cache hits and a processor configured to execute the instruction stored in the storage unit. When the instruction is executed, the processor is configured to generate prefetcher friendly data by filtering the prefetcher data, set a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory based on the prefetcher friendly data, and determine whether data of the first pointer area and the second pointer area are migrated, in consideration of a reference bit and the prefetcher friendly bit of the first and second pointer areas.