公开(公告)号：US20240311302A1

公开(公告)日：2024-09-19

申请号：US18589852

申请日：2024-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Jung ,  Daehoon Kim ,  Hwanjun Lee ,  Jonggeon Lee ,  Jinin So

IPC: G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0811 ,  G06F12/084

Abstract: A processor includes a processing core configured to process each of a plurality of requests by accessing a corresponding one of a first memory and a second memory, a latency monitor configured to generate first latency information and second latency information, the first latency information comprising a first access latency to the first memory, and the second latency information comprising a second access latency to the second memory, a plurality of cache ways divided into a first partition and a second partition, and a decision engine configured to allocate each of the plurality of cache ways to one of the first partition and the second partition, based on the first latency information and the second latency information.

公开(公告)号：US11620135B2

公开(公告)日：2023-04-04

申请号：US17115924

申请日：2020-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonggeon Lee ,  Kyungsoo Kim ,  Jinin So ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F9/00 ,  G06F9/4401 ,  G06N20/00

Abstract: A booting method of a computing system, which includes a memory module including a processing device connected to a plurality of memory devices, including: powering up the computing system; after powering up the computing system, performing first memory training on the plurality of memory devices by the processing device in the memory module, and generating a module ready signal indicating completion of the first memory training; after powering up the computing system, performing a first booting sequence by a host device, the host device executing basic input/output system (BIOS) code of a BIOS memory included in the computing system; waiting for the module ready signal to be received from the memory module in the host device after performing the first booting sequence; and receiving the module ready signal in the host device, and performing a second booting sequence based on the module ready signal.

公开(公告)号：US12223188B2

公开(公告)日：2025-02-11

申请号：US17748564

申请日：2022-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna Talanki ,  Archita Khare ,  Rahul Tarikere Ravikumar ,  Jinin So ,  Jonggeon Lee

IPC: G06F3/06 ,  G06F12/1027

Abstract: A memory interface for interfacing with a memory device includes a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred.

公开(公告)号：US12079146B2

公开(公告)日：2024-09-03

申请号：US17383056

申请日：2021-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyeon Cho ,  Yongsuk Kwon ,  Kyungsoo Kim ,  Jonghoon Kim ,  Jonghyun Seok ,  Jonggeon Lee

IPC: H05K1/02 ,  G06F1/20 ,  G06F1/30 ,  G06F13/12 ,  G06F13/16 ,  G06F13/364 ,  G06F13/40 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/36 ,  H05K7/02 ,  H05K7/20

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G06F13/409 ,  G11C5/06 ,  G11C7/1063

Abstract: A memory module includes a memory substrate including a main connector and an auxiliary connector, configured to be connected to an external device; and a plurality of memory chips mounted on at least one of a first surface or a second surface of the memory substrate, wherein the main connector is disposed on one side of the memory substrate, and the auxiliary connector is disposed on the second surface of the memory substrate.

公开(公告)号：US20220027090A1

公开(公告)日：2022-01-27

申请号：US17154030

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsuk Kwon ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F3/06 ,  G06F1/08

Abstract: Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.

公开(公告)号：US12272423B2

公开(公告)日：2025-04-08

申请号：US17974940

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sachin Suresh Upadhya ,  Eldho Pathiyakkara Thombra Mathew ,  Mayuresh Jyotindra Salelkar ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.

公开(公告)号：US20230386534A1

公开(公告)日：2023-11-30

申请号：US17974940

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sachin Suresh Upadhya ,  Eldho Pathiyakkara Thombra Mathew ,  Mayuresh Jyotindra Salelkar ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1069 ,  G11C7/1066 ,  G11C7/227 ,  G11C7/1063

Abstract: A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.

公开(公告)号：US20230028071A1

公开(公告)日：2023-01-26

申请号：US17715158

申请日：2022-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonggeon Lee ,  Jinin So ,  Yongsuk Kwon ,  Kyungsoo Kim ,  Ilkwon Yun ,  Jeonghyeon Cho

IPC: G06F13/40 ,  G06F13/16 ,  G06F9/30

Abstract: A memory module includes a device memory configured to store data and including a first memory area and a second memory area, and a controller including an accelerator circuit. The controller is configured to control the device memory, transmit a command to exclude the first memory area from the system memory map to a host processor in response to a mode change request, and modify a memory configuration register to exclude the first memory area from the memory configuration register. The accelerator circuit is configured to use the first memory area to perform an acceleration operation.

公开(公告)号：US11531496B2

公开(公告)日：2022-12-20

申请号：US17154030

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsuk Kwon ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F3/06 ,  G06F1/08

Abstract: Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.

公开(公告)号：US10957414B1

公开(公告)日：2021-03-23

申请号：US16862964

申请日：2020-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngman Ahn ,  Sangyeol Lee ,  Jonggeon Lee

IPC: G11C29/44 ,  G11C29/46 ,  G11C29/12 ,  G11C29/50

Abstract: A method and a memory device for testing and repairing memory cells during a power-up sequence are provided. The memory device includes a built-in self test (BIST) unit for testing a memory cell array during the power-up sequence. The BIST unit performs a test on the memory cell array in response to a power stabilization signal, or performs a test on the memory cell array in response to an impedance control (ZQ) calibration command. The BIST unit terminates a test being performed in response to a write leveling command, or terminates a test being performed in response to an active command.