公开(公告)号：US20240413245A1

公开(公告)日：2024-12-12

申请号：US18666932

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Namgung ,  Hwasung Rhee ,  Youngshil Kim ,  Hyokyeom Kim ,  Joonil Cha

IPC: H01L29/78 ,  H01L23/00

Abstract: A semiconductor device includes a substrate having a first region and a second region surrounding the first region, an integrated circuit structure disposed on the first region, and a seal ring structure disposed on the second region, wherein the integrated circuit structure includes a first active fin extending on the first region in a crystal direction of the substrate, a first epitaxial pattern disposed on one region of the first active fin, and a first contact structure connected to the first epitaxial pattern, and the seal ring structure includes a second active fin extending on the second region in a crystal direction of the substrate, a second epitaxial pattern disposed on the second active fin and including the same material as that of the first epitaxial pattern, and a second contact structure connected to the second epitaxial pattern.

公开(公告)号：US09337112B2

公开(公告)日：2016-05-10

申请号：US14725603

申请日：2015-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ping Hsun Su ,  Yoonhae Kim ,  Hwasung Rhee

IPC: H01L21/8234 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

公开(公告)号：US20250120114A1

公开(公告)日：2025-04-10

申请号：US18663238

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolsoon Jeong ,  Sangjung Kang ,  Jido Ryu ,  Hwasung Rhee ,  Hochul Lim

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: An integrated circuit semiconductor device includes an active fin on a substrate, gate structures apart from one another on the active fin, an interlayer insulation layer to insulate the gate structures on the active fin, gate contacts apart from one another on the gate structures, active contacts apart from one another at both sides of the gate structures, the active contacts passing through the interlayer insulation layer and contacting the active fin, an etch stopping layer on the gate structures, the interlayer insulation layer, the gate contacts, and the active contacts, and diffusion break regions between the active contacts, the diffusion break regions being buried in gate trenches passing through the etch stopping layer and the interlayer insulation layer and in fin recesses cutting the active fin under the gate trenches.

公开(公告)号：US11637065B2

公开(公告)日：2023-04-25

申请号：US17648829

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miji Lee ,  Taeyoung Jeong ,  Yoonkyeong Jo ,  Sangwoo Pae ,  Hwasung Rhee

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.

公开(公告)号：US10128243B2

公开(公告)日：2018-11-13

申请号：US14955107

申请日：2015-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min Yoo ,  Sangyoon Kim ,  Woosik Kim ,  Jongmil Youn ,  Hwasung Rhee ,  Heedon Jeong

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.

公开(公告)号：US11239162B2

公开(公告)日：2022-02-01

申请号：US16877945

申请日：2020-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miji Lee ,  Taeyoung Jeong ,  Yoonkyeong Jo ,  Sangwoo Pae ,  Hwasung Rhee

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.

公开(公告)号：US20160020159A1

公开(公告)日：2016-01-21

申请号：US14725603

申请日：2015-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ping Hsun Su ,  Yoonhae Kim ,  Hwasung Rhee

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

Abstract translation: 提供半导体器件。 第一和第二焊盘电连接到多个测试结构。 每个测试结构包括有源区，有源图案，栅电极和电极图案。 活动区域包括圆角部分。 有源图案从半导体衬底突出并沿第一方向平行延伸。 栅电极在第二方向上跨过有源图案。 一个栅电极电连接到第一焊盘。 电极图案设置在与第一焊盘电连接的栅电极的一侧。 电极图案电连接到第二垫。 电极图案穿过有源图案。 每个测试结构中的电极图案和活性图案的重叠区域与其他测试结构中的电极图案和活动图案的重叠区域不同。

公开(公告)号：US09082739B2

公开(公告)日：2015-07-14

申请号：US14261513

申请日：2014-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ping Hsun Su ,  Yoonhae Kim ,  Hwasung Rhee

IPC: H01L21/8234 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

Abstract translation: 提供半导体器件。 第一和第二焊盘电连接到多个测试结构。 每个测试结构包括有源区，有源图案，栅电极和电极图案。 活动区域包括圆角部分。 有源图案从半导体衬底突出并沿第一方向平行延伸。 栅电极在第二方向上跨过有源图案。 一个栅电极电连接到第一焊盘。 电极图案设置在与第一焊盘电连接的栅电极的一侧。 电极图案电连接到第二垫。 电极图案穿过有源图案。 每个测试结构中的电极图案和活性图案的重叠区域与其他测试结构中的电极图案和活动图案的重叠区域不同。