公开(公告)号：US11024364B2

公开(公告)日：2021-06-01

申请号：US16555089

申请日：2019-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Seo ,  Dong-Il Lee ,  Hye-Jung Kwon

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/56 ,  G11C11/4093 ,  G11C7/06

Abstract: There are provided a sense amplifier for sensing a multilevel cell and a memory device including the same. The sense amplifier is configured to sense the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data a cell voltage stored in a memory cell as the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data. The sense amplifier senses the MSB of the 2-bit data in a state in which a bit line is electrically disconnected from a holding bit line of the sense amplifier and senses the LSB of the 2-bit data in a state in which the cell bit line is electrically connected to the holding bit line. The sense amplifier is configured to equalize a pair of bit lines of the sense amplifier before sensing the MSB and the LSB of the 2-bit data. The sense amplifier is configured to restore to the memory cell the cell voltage corresponding to the sensed MSB and LSB of the 2-bit data.

公开(公告)号：US10649849B2

公开(公告)日：2020-05-12

申请号：US15938092

申请日：2018-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Hun Kim ,  Su-Yeon Doo ,  Dong-Seok Kang ,  Hye-Jung Kwon ,  Young-Ju Kim

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/10 ,  H03K3/84 ,  H03K3/03

Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.