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公开(公告)号：US11194657B2
公开(公告)日：2021-12-07
申请号：US16823443
申请日：2020-03-19
发明人： Sang-Uhn Cha , Kyung-Ryun Kim , Young-Hun Seo
IPC分类号： G06F11/10 , G11C29/52 , G11C11/4093 , G11C11/4096 , H01L25/065 , G11C11/407 , G11C5/04
摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.
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公开(公告)号：US11024364B2
公开(公告)日：2021-06-01
申请号：US16555089
申请日：2019-08-29
发明人： Young-Hun Seo , Dong-Il Lee , Hye-Jung Kwon
IPC分类号： G11C11/40 , G11C11/4091 , G11C11/56 , G11C11/4093 , G11C7/06
摘要： There are provided a sense amplifier for sensing a multilevel cell and a memory device including the same. The sense amplifier is configured to sense the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data a cell voltage stored in a memory cell as the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data. The sense amplifier senses the MSB of the 2-bit data in a state in which a bit line is electrically disconnected from a holding bit line of the sense amplifier and senses the LSB of the 2-bit data in a state in which the cell bit line is electrically connected to the holding bit line. The sense amplifier is configured to equalize a pair of bit lines of the sense amplifier before sensing the MSB and the LSB of the 2-bit data. The sense amplifier is configured to restore to the memory cell the cell voltage corresponding to the sensed MSB and LSB of the 2-bit data.
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3.发明授权公开(公告)号：US10854277B2
公开(公告)日：2020-12-01
申请号：US16888006
申请日：2020-05-29
发明人： Young-Hun Seo , Kyung-Ryun Kim
IPC分类号： G11C7/00 , G11C11/4091 , G11C11/56
摘要： A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.
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4.发明授权公开(公告)号：US10573356B2
公开(公告)日：2020-02-25
申请号：US15851197
申请日：2017-12-21
发明人： Sang-Uhn Cha , Young-Hun Seo , Kwang-Il Park , Seung-Jun Bae
IPC分类号： G06F11/00 , G11C7/10 , G11C11/4093 , G11C11/4096 , H03M13/00 , G06F11/10
摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.
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5.发明授权公开(公告)号：US11216339B2
公开(公告)日：2022-01-04
申请号：US17105205
申请日：2020-11-25
发明人： Young-Hun Seo , Kwang-Il Park , Seung-Jun Bae , Sang-Uhn Cha
IPC分类号： G06F11/00 , G06F11/10 , G11C29/52 , G11C11/4093 , H01L25/065
摘要： A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.
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6.发明授权公开(公告)号：US10884852B2
公开(公告)日：2021-01-05
申请号：US16228560
申请日：2018-12-20
发明人： Young-Hun Seo , Kwang-Il Park , Seung-Jun Bae , Sang-Uhn Cha
IPC分类号： G06F11/00 , G06F11/10 , G11C29/52 , G11C11/4093 , H01L25/065
摘要： A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.
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7.发明授权公开(公告)号：US10706911B1
公开(公告)日：2020-07-07
申请号：US16156052
申请日：2018-10-10
发明人： Young-Hun Seo , Kyung-Ryun Kim
IPC分类号： G11C7/00 , G11C11/4091 , G11C11/56
摘要： A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.
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8.发明授权Circuit for controlling sense amplifier source node in semiconductor memory device and controlling method thereof 有权用于控制半导体存储器件中的读出放大器源节点的电路及其控制方法公开(公告)号：US09147465B2
公开(公告)日：2015-09-29
申请号：US14139736
申请日：2013-12-23
发明人： Young-Hun Seo , Chul-Sung Park , Young-Dae Lee
IPC分类号： G11C11/4091
CPC分类号： G11C11/4091
摘要： Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level. The sense amplifier source node control circuit may also include: a floating circuit for floating the sense amplifier driving signal line in a set operating mode; and a controller connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, for controlling a level of the sense amplifier driving signal line in the set operating mode.
摘要翻译： 提供了半导体存储器件的位线读出放大器源节点控制电路。 感测放大器源节点控制电路可以包括连接在读出放大器的源节点和读出放大器驱动信号线之间的源极驱动器，用于将读出放大器的源极节点驱动到设定的电压电平。 感测放大器源节点控制电路还可以包括：用于在设定的工作模式下浮置读出放大器驱动信号线的浮置电路; 以及与感测放大器的源极节点和感测放大器驱动信号线之间的源极驱动器并联连接的控制器，用于在设定的工作模式下控制读出放大器驱动信号线的电平。
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