公开(公告)号：US20190103407A1

公开(公告)日：2019-04-04

申请号：US16038052

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/0688 ,  H01L27/1085 ,  H01L28/86

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US20200111793A1

公开(公告)日：2020-04-09

申请号：US16707019

申请日：2019-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/06

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US20210057416A1

公开(公告)日：2021-02-25

申请号：US17090419

申请日：2020-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US20190164985A1

公开(公告)日：2019-05-30

申请号：US16027887

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Junsoo KIM ,  Hui-Jung KIM ,  Bong-Soo KIM ,  Satoru YAMADA ,  Kyupil LEE ,  Sunghee HAN ,  HyeongSun HONG ,  Yoosang HWANG

IPC: H01L27/11556 ,  H01L23/532 ,  H01L27/11524 ,  H01L49/02 ,  G11C8/14 ,  G11C7/18

Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US20150001617A1

公开(公告)日：2015-01-01

申请号：US14488426

申请日：2014-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik KIM ,  HyeongSun HONG ,  Yongchul OH ,  Yoosang HWANG

IPC: H01L27/105 ,  H01L23/538 ,  H01L29/51 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L27/1052 ,  H01L23/5386 ,  H01L27/088 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/515 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.

Abstract translation: 制造半导体器件的方法可以包括在衬底中形成第一沟槽以限定鳍片图案并形成填充第一沟槽的较低区域的埋入电介质图案。 第一个沟槽并行延伸。 栅电介质层形成在第一沟槽的上内侧壁上，并且在包括栅极电介质层的衬底上形成填充第一沟槽的栅极导电层。 栅极导电层，栅极电介质层和鳍状图案被图案化以形成与第一沟槽交叉并限定有源支柱的第二沟槽。 还可以提供半导体器件。