公开(公告)号：US12259817B2

公开(公告)日：2025-03-25

申请号：US17403862

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeok Jun Choe ,  Youn Ho Jeon ,  Young Geon Yoo ,  Hyo-Deok Shin ,  I Poom Jeong

IPC: G06F12/0877 ,  G06F13/28

Abstract: A smart storage device is provided. The smart storage device includes a smart interface connected to a host device. An accelerator circuit is connected to the smart interface through a data bus conforming to a CXL.cache protocol and a CXL.mem protocol. The accelerator circuit is configured to perform acceleration computation in response to a computation command of the host device. A storage controller is connected to the smart interface through a data bus conforming to a CXL.io protocol. The storage controller is configured to control a data access operation for a storage device in response to a data access command of the host device. The accelerator circuit is directly accessible to the storage device through an internal bus connected directly to the storage controller.

公开(公告)号：US20220100669A1

公开(公告)日：2022-03-31

申请号：US17403862

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeok Jun Choe ,  Youn Ho Jeon ,  Young Geon Yoo ,  Hyo-Deok Shin ,  I Poom Jeong

IPC: G06F12/0877 ,  G06F13/28

Abstract: A smart storage device is provided. The smart storage device includes a smart interface connected to a host device. An accelerator circuit is connected to the smart interface through a data bus conforming to a CXL.cache protocol and a CXL.mem protocol. The accelerator circuit is configured to perform acceleration computation in response to a computation command of the host device. A storage controller is connected to the smart interface through a data bus conforming to a CXL.io protocol. The storage controller is configured to control a data access operation for a storage device in response to a data access command of the host device. The accelerator circuit is directly accessible to the storage device through an internal bus connected directly to the storage controller.

公开(公告)号：US10929064B2

公开(公告)日：2021-02-23

申请号：US16443551

申请日：2019-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin Cho ,  Hee Hyun Nam ,  Hyo-Deok Shin ,  Junghwan Ryu

IPC: G06F3/06 ,  G11C16/10

Abstract: An operational method of a memory module is provided. The method includes receiving, from an external of the memory module, a first command and a first address in synchronization with clock signals. Status information is output through a signal line, when first data corresponding the first address is available in a data buffer in response to the first command. A second command in synchronization with the clock signals after the transmitting the status information is received from the external of the memory module, a second command. In response to the second command, the first data being available in the data buffer is output through data lines.

公开(公告)号：US10331378B2

公开(公告)日：2019-06-25

申请号：US15188183

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjin Cho ,  Hee Hyun Nam ,  Hyo-Deok Shin ,  Junghwan Ryu

IPC: G06F3/06 ,  G06F12/06 ,  G11C16/10

Abstract: A method of operating a memory module can include receiving, at the memory module, an active command and an associated row address that indicates that the active command is directed to a volatile memory device included in the memory module or to a non-volatile memory device included in the memory module. The volatile memory device or the non-volatile memory device can be activated based on the associated row address in response to the active command. Status information can be provided at the memory module indicating readiness of the memory module for receipt of an operation command associated with the active command and the associated row address.

公开(公告)号：US11226823B2

公开(公告)日：2022-01-18

申请号：US16879120

申请日：2020-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younho Jeon ,  Youngjin Cho ,  Hee Hyun Nam ,  Hyo-Deok Shin

IPC: G06F9/30 ,  G06F1/12 ,  G06K9/62 ,  G06F12/02 ,  G06F9/54 ,  G06F1/08

Abstract: A memory module includes a device controller that communicates with a host device based on a first interface including a first clock signal, a first data signal, and a first data strobe signal and operates in one of a first operation mode or a second operation mode depending on an operation mode control value from the host device, and a memory device that communicates with the device controller based on a second interface including a second data signal and a second data strobe signal. The device controller includes a logic circuit that transmits a predetermined training result value to the host device depending on a training control value from the host device, when a training is performed on a third interface being a virtual interface recognized by the host device in the first operation mode.

公开(公告)号：US09799402B2

公开(公告)日：2017-10-24

申请号：US15083834

申请日：2016-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Kim ,  Seong Yeon Kim ,  Jaegeun Park ,  Hyo-Deok Shin ,  Younggeun Lee ,  Youngjin Cho

IPC: G11C16/10 ,  G11C7/10

CPC classification number: G11C16/10 ,  G11C7/1063

Abstract: A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile memory devices through one channel. During a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel. While the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.